m52d128168a Elite Semiconductor Memory Technology Inc., m52d128168a Datasheet - Page 15

• Manufacturer Part Number: m52d128168a
• Description: 2m X 16 Bit X 4 Banks Mobile Synchronous Dram
• Manufacturer: Elite Semiconductor Memory Technology Inc.

Precharge command
(BS). When A10 is High, all banks are precharged, regardless of BA1 and BA0. When
A10 is Low, only the bank selected by BA1 and BA0 is precharged.
precharging bank during t
This command corresponds to a conventional DRAM’s RAS rising.
Write command
address given by the column address to begin the burst write operation. The first write
data in burst can be input with this command with subsequent data on following
clocks.
Read command
This command sets the burst start address given by the column address.
Elite Semiconductor Memory Technology Inc.
This command begins precharge operation of the bank selected by BA1 and BA0
After this command, the DRAM can’t accept the activate command to the
If the mode register is in the burst write mode, this command sets the burst start
Read data is available after CAS latency requirements have been met.
( CS , RAS , WE = Low, CAS = High )
( CS , CAS , WE = Low, RAS = High)
( CS , CAS = Low, RAS , WE = High)
RP
(precharge to activate command period).
Publication Date: Aug. 2009
Revision: 1.3
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