m52d128168a Elite Semiconductor Memory Technology Inc., m52d128168a Datasheet - Page 5

• Manufacturer Part Number: m52d128168a
• Description: 2m X 16 Bit X 4 Banks Mobile Synchronous Dram
• Manufacturer: Elite Semiconductor Memory Technology Inc.

AC OPERATING TEST CONDITIONS
Output
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
Elite Semiconductor Memory Technology Inc.
RAS to CAS delay
Row active time
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Row active to row active delay
Row precharge time
Row cycle time
Last data in to new col. Address delay
Last data in to row precharge
Last data in to burst stop
Col. Address to col. Address delay
Mode Register command to Active or Refresh
Command
Refresh period(4,096 rows)
Number of valid output
data
10.6K
5. A new command may be given t
6. A maximum of eight consecutive AUTO REFRESH commands (with t
3. Minimum delay is required to complete write.
4. All parts allow every cycle column address change.
5. In case of row precharge interrupt, auto precharge and read burst stop.
(Fig.1) DC Output Load circuit
then rounding off to the next higher integer.
The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks
the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is
8x15.6μs.)
Parameter
Parameter
1.8V
13.9K
20 pF
VOH(DC) = VDDQ-0.2V, IOH = -0.1mA
VOL(DC) = 0.2V, IOL = 0.1mA
@Operating
@Auto refresh
CAS latency=3
CAS latency=2
RFC
after self refresh exit.
(V
DD
=1.8V
t
t
t
t
t
t
t
t
Symbol
t
t
t
RAS
REF
RRD
RCD
t
t
CCD
MRD
RAS
RFC
CDL
RDL
BDL
RP
RC
(min)
(min)
(max)
(max)
(min)
(min)
(min)
(min)
(min)
(min)
(min)
(min)
(min)
±
0.1V, T
Output
A
0.9 x V
= 0 C
tr / tf = 1 / 1
0.5 x V
0.5 x V
See Fig.2
14
14
14
42
63
-7
° ~ 70 C
Value
DDQ
(Fig.2) AC Output Load Circuit
DDQ
DDQ
RFCmin
/ 0.2
° )
Z0=50
Version
) can be posted to any given SDRAM, and
67.5
-7.5
100
15
15
15
48
80
64
1
2
1
1
2
2
1
Publication Date: Aug. 2009
Revision: 1.3
M52D128168A
Vtt =0.5x VDDQ
20 pF
-10
50
20
20
20
50
90
Unit
Unit
CLK
CLK
CLK
CLK
CLK
ns
ms
V
V
V
ea
ns
ns
ns
ns
us
ns
ns
Note
1 , 5
5/48
1
1
1
1
1
2
2
2
3
6
4
-
-