m52d128168a Elite Semiconductor Memory Technology Inc., m52d128168a Datasheet - Page 14

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m52d128168a

Manufacturer Part Number
m52d128168a
Description
2m X 16 Bit X 4 Banks Mobile Synchronous Dram
Manufacturer
Elite Semiconductor Memory Technology Inc.
Datasheet
COMMANDS
Mode register set command
command, A0 through BA0 are the data input pins. After power on, the mode register
set command must be executed to initialize the device.
(t
Extended Mode register set command
Activate command
address selected by A0 through A11.
Elite Semiconductor Memory Technology Inc.
MRD
The DRAM has a mode register that defines how the device operates. In this
The mode register can be set only when all banks are in idle state. During 2CLK
The DRAM has an extended mode register that defines how to set PASR, DS.
The DRAM has four banks, each with 4,096 rows.
This command activates the bank selected by BA1 and BA0 (BS) and a row
This command corresponds to a conventional DRAM’s RAS falling.
) following this command, the DRAM cannot accept any other commands.
(
( CS , RAS , CAS , WE , BA0 = Low ; BA1= High)
( CS , RAS = Low, CAS , WE = High)
CS
,
RAS
,
CAS
,
WE
,
BA1, BA0 = Low)
Publication Date: Aug. 2009
Revision: 1.3
M52D128168A
14/48

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