SDA9410-B13 MICRONAS [Micronas], SDA9410-B13 Datasheet - Page 17

• Manufacturer Part Number: SDA9410-B13
• Description: Display Processor and Scan Rate Converter using Embedded DRAM Technology Units
• Manufacturer: MICRONAS [Micronas]

SDA9410
Table 1
Symbol
17
VSSLx *)
VDDLx
VSSPx
VDDPx
VSSE1
VDDEx
VSSAx
VDDAx
YINM 0...7
UVINM 0...7
YINS 0...7
UVINS 0...7
RESET
HINM
VINM
SYNCENM
HINS
VINS
SYNCENS
SDA
SCL
BLANK
VOUT
HOUT
Pin
Num.
8,13,15,16,
22,23,75
9,12, 68,74
10,17,29,43,
57, 70, 79,
100
11,21,36,54,
69, 80,99
67
14,66
19,59,92,96,
98
20,60, 95,97 S
39,...,42;
44,...,47
30,...,35;
37; 38
61,...,65;
71,...,73
48,..,53;
55;56
81
27
26
28
77
78
76
24
25
7
5
4
Pin definitions and functions
Input
Outp.
S
S
S
S
S
S
S
I/TTL
I/TTL PD Data input UV master channel
I/TTL PD Data input Y slave channel
I/TTL PD Data input UV slave channel
I/TTL
I/TTL
PD
I/TTL
PD
I/TTL
I/TTL
PD
I/TTL
PD
I/TTL
IO
I
O/TTL
O/TTL
O/TTL
Function
Supply voltage for digital logic parts ( V
Supply voltage for digital logic parts ( V
Supply voltage for pads ( V
Supply voltage for pads ( V
Supply voltage for embedded DRAM ( V
Supply voltage for embedded DRAM ( V
Supply voltage for analog PLL and for analog parts DAC ( V
Supply voltage for analog PLL and for analog parts DAC
( V
Data input Y master channel
System reset. The RESET input is low active. In order to ensure
correct operation a "Power On Reset" must be performed. The
RESET pulse must have a minimum duration of two clock periods of
the master (CLKM) and slave clock (CLKS), respectively.
H-Sync input master channel
V-Sync input master channel
Synchronization enable input master channel
H-Sync input slave channel
V-Sync input slave channel
Synchronization enable input slave channel
I
I
Blanking signal
V-Sync output
H-Sync output
2
2
C-Bus data line
C-Bus clock line
DD
= 3.3 V )
SS
DD
= 0 V )
= 3.3 V )
SS
DD
SS
DD
= 0 V )
Preliminary Data Sheet
= 3.3 V )
= 0 V )
= 3.3 V )
Pin Description
Micronas
SS
= 0 V )