SDA9410-B13 MICRONAS [Micronas], SDA9410-B13 Datasheet - Page 67

• Manufacturer Part Number: SDA9410-B13
• Description: Display Processor and Scan Rate Converter using Embedded DRAM Technology Units
• Manufacturer: MICRONAS [Micronas]

SDA9410
signalizes the progressing shifting operation.
It is recommended to enable the registers RSHFTM and RSHFTS in all application
modes.
5.6.6
This chapter describes the I²C Bus parameters to get a joint line free display in SSC
mode.
Table 59
Table 60
A special circuit is implemented to achieve a joint line free display in SSC mode (e.g.
Double Window Display). This circuit synchronizes the two input sources and removes
the joint lines by automatic controlled shifting of the display raster phase. This procedure
enlarges the value of OPDELM resulting in an delayed start of the output processing.
The I²C Bus parameters RSHFTM and RSHFTS enable joint line free display for master
and slave channel, separately. SHFTSTEP fixes the amount of lines which is added to
OPDELM with each output frame. The readable I²C Bus parameter SHIFTACT
67
I²C Bus
parameter
SHIFTACT
I²C Bus
parameter
[Default]
RSHFTM
[0]
RSHFTS
[0]
SHFTSTEP
[0100]
PROG_THRES
[0111100]
Joint line free display
Input write I²C Bus parameter
Output read I²C Bus parameter
Description
indicates active shifting process of the display raster phase
0: display phase shifting not active
1: display phase shift active
Sub address
55h
55h
55h
56h
Description
Joint line free display of master channel by shifting the output raster
phase (SSC-Mode)
1: enabled
0: disabled
Joint line free display of master and slave channel by shifting the
output raster phase (SSC-Mode, RSHFTM=1)
1: enabled
0: disabled
Increment for raster phase shift per output frame (lines)
Threshold to display progressive PIP without joint lines
Application modes and memory concept
Preliminary Data Sheet
Micronas