SDA9410-B13 MICRONAS [Micronas], SDA9410-B13 Datasheet - Page 22

• Manufacturer Part Number: SDA9410-B13
• Description: Display Processor and Scan Rate Converter using Embedded DRAM Technology Units
• Manufacturer: MICRONAS [Micronas]

SDA9410
5.2
Table 2
The input sync controller derives framing signals from the H- and V-Sync for the input
data processing. The framing signals depend on different I²C Bus parameters and mark
the active picture area.
Figure 7
The distance between the incoming H-syncs in system clocks of CLKM/CLKS must be
even.
22
Signals
HINM
VINM
SYNCENM
HINS
VINS
SYNCENS
VINM
Input sync controller (ISCM/ISCS)
Input signals
Input I²C Bus parameter
Pin number
27
26
28
77
78
76
HINM
lines
field
per
NAPIPPHM+PD)*
(NAPIPDLM*4 +
CLKM
Description
horizontal synchronization signal (polarity programmable, I²C Bus
parameter 11h HINPOLM, default: high active)
vertical synchronization signal (polarity programmable, I²C Bus
parameter 11h VINPOLM, default: high active)
enable signal for HINM and VINM signal, low active ("Input format
conversion (IFCM/IFCS)" on page 26)
horizontal synchronization signal (polarity programmable, I²C Bus
parameter 33h HINPOLS, default: high active)
vertical synchronization signal (polarity programmable, I²C Bus
parameter 33h VINPOLS, default: high active)
enable signal for HINS and VINS signal, low active ("Input format
conversion (IFCM/IFCS)" on page 26)
(APPLIPM*8)*CLKM
pixels per line
PD - Processing Delay
Input sync controller (ISCM/ISCS)
Preliminary Data Sheet
(ALPFIPM*2)
NALIPM + PD
Micronas