FWIXEPAD0SE001 INTEL [Intel Corporation], FWIXEPAD0SE001 Datasheet - Page 108

• Manufacturer Part Number: FWIXEPAD0SE001
• Description: Advanced 8-Port 10/100 Mbps PHY Transceivers
• Manufacturer: INTEL [Intel Corporation]

LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
110
Table 39. Intel
Designation
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
BGA15 Ball
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-
Down.
®
M2,
M3,
M1,
N3,
K2,
H3,
E3,
B4,
H2,
C2,
A4,
F2,
G1
J2,
F3,
C5
K1
E1
C6
N5
P5
J3
LXT9785 BGA15 Signal Descriptions (Sheet 2 of 7)
RxData0_SS
RxData1_SS
RxData2_SS
RxData3_SS
RxData4_SS
RxData5_SS
RxData6_SS
RxData7_SS
RxData0_S
RxData1_S
RxData2_S
RxData3_S
RxData4_S
RxData5_S
RxData6_S
RxData7_S
RxSYNC
TxSYNC
Symbol
RxCLK
MDINT
TxCLK
MDIO
MDIO Control Interface Signal Descriptions
SS-SMII Specific Signal Descriptions
OD, TS,
I/O, TS,
O, TS,
O, TS,
O, TS,
SL, IP
O, TS
Type
I, ID
I, ID
SL,
ID
ID
ID
IP
Signal Description
Receive Data - Ports 0-7.
These serial output streams provide data received from the
network. The LXT9785/9785E drives the data out
synchronously to REFCLK.
SS-SMII Transmit Synchronization.
The MAC must generate a TxSYNC pulse every 10 TxCLK
cycles to mark the start of TxData segments.
SS-SMII Receive Synchronization.
The LXT9785/9785E generates these pulses every 10
RxCLK cycles to mark the start of RxData segments for the
MAC.
SS-SMII Transmit Clock.
The MAC sources this 125 MHz clock as the timing
reference for TxData and TxSYNC.
Requirements” on page 125
SS-SMII Receive Clock.
The LXT9785/9785E generates these clocks, based on
REFCLK, to provide a timing reference for RxData and
RxSYNC to the MAC.
page 125
only enabled when SS-SMII mode is enabled.
Receive Data - Ports 0-7.
These serial output streams provide data received from the
network. The LXT9785/9785E drives the data out
synchronously to REFCLK.
Management Data Input/Output.
Bidirectional serial data channel for communication
between the PHY and MAC or switch ASIC. Refer to
Figure 21 on page
Management Data Interrupt.
When Register bit 18.1 = 1, an active Low output on this
Pin indicates status change. Refer to
for detailed clock
140.
See “Clock/SYNC Requirements” on
for detailed clock requirements.
requirements.
Revision Date: August 28, 2003
Document Number: 249241
See “Clock/SYNC
Figure 21 on page
Revision Number: 007
These outputs are
Datasheet
140.