FWIXEPAD0SE001 INTEL [Intel Corporation], FWIXEPAD0SE001 Datasheet - Page 205

• Manufacturer Part Number: FWIXEPAD0SE001
• Description: Advanced 8-Port 10/100 Mbps PHY Transceivers
• Manufacturer: INTEL [Intel Corporation]

Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Table 91. Auto-Negotiation Link Partner Next Page Receive Register (Address 8)
Table 92. Port Configuration Register (Address 16, Hex 10) (Sheet 1 of 2)
1. R = Read Only
2. Default value at the start of auto-negotiation code word transmission.
1. R/W = Read/Write
2. LSHR = Default value is derived from a single device input pin state or a group of device input pin states as
3. The default value of Register bit 16.0 is determined by the G_FX/TP pin.
4. The default value of Register bit 16.5 is determined by the PREASEL pin. The BGA15 package does not
5. The BGA15 package does not support fiber. Default for the BGA15 package is 0.
6. NA means the bits do not have a default value and may initially contain any value.
10:0
Bit
15
14
13
12
11
Bit
15
14
13
12
10
11
the pin(s) are latched at startup or hardware reset.
If G_FX/TP is tied Low, the default value of Register bit 16.0 = 0. If G_FX/TP is not tied Low, the default
value of Register bit 16.0 = 1. The BGA15 package does not have a G_FX/TP hardware configuration pin.
have a PREASEL hardware configuration pin and has a default of 0.
Name
Next Page
(NP)
Acknowledge
(ACK)
Message Page
(MP)
Acknowledge 2
(ACK2)
Toggle
(T)
Message/
Unformatted
Code Field
Name
Reserved
Link Disable
Transmit Disable
Bypass Scramble
(100BASE-TX)
Reserved
Jabber
(10BASE-T)
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Description
0 = Link partner has no additional next pages to send
1 = Link partner has additional next pages to send
0 = Link partner has not received Link Code Word from
1 = Link partner has received Link Code Word from the
0 = Page sent by the link partner is an unformatted page
1 = Page sent by the link partner is a message page
0 = Link partner cannot comply with the message
1 = Link partner complies with the message
0 = Previous value of the transmitted Link Code Word
1 = Previous value of the transmitted Link Code Word
MP = 1: Code interpreted as message page
MP = 0: Code interpreted as unformatted page
Description
Write as 0, ignore on Read
0 = Normal operation
1 = Force link pass (sets appropriate registers and LEDs
Note: Setting this bit in 100 Mbps mode by-passes the
descrambler lock requirement to establish link and forces
the link to the link-good state. Setting this bit produces
unreliable results if the descrambler is not locked,
0 = Normal operation
1 = Disable twisted-pair transmitter
0 = Normal operation
1 = Bypass scrambler and descrambler
Write as 0, ignore on Read
0 = Normal operation
1 = Jabber function is enabled; however, jabber status
the LXT9785/LXT9785E
LXT9785/LXT9785E
equalled logic one
equalled logic zero
to pass)
reporting to Register bit 1.1 is disabled
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
1
1
Default
Default
0x000
0
0
0
0
0
0
0
0
0
0
0
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