FWIXEPAD0SE001 INTEL [Intel Corporation], FWIXEPAD0SE001 Datasheet - Page 41

• Manufacturer Part Number: FWIXEPAD0SE001
• Description: Advanced 8-Port 10/100 Mbps PHY Transceivers
• Manufacturer: INTEL [Intel Corporation]

Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Table 12. Intel
Table 13. Intel
1. Type Column Coding: I = Input, O = Output, OD = Open Drain, TS = Three-State-able output, SMT =
2. The IP/ID resistors are disabled during H/W Power-Down mode. If a pin is an output or an I/O, the IP/ID
3. TDO output is three-stated in H/W Power-Down mode and during H/W reset.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain Output, ST = Schmitt Triggered Input, TS =
2. The IP/ID resistors are disabled during hardware power-down mode.
PQFP
PQFP
167
168
169
170
171
Schmitt Triggered input, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-
Down.
resistors are also disabled when the output is enabled.
94
93
Three-State-able Output, SL = Slew-rate Limited Output, IP = Weak Internal Pull-Up, ID = Weak Internal
Pull-Down.
Designation
Designation
®
®
Pin/Ball
Pin/Ball
LXT9785/LXT9785E JTAG Test Signal Descriptions – PQFP
LXT9785/LXT9785E Miscellaneous Signal Descriptions – PQFP (Sheet 1 of 4)
PBGA
PBGA
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
M16
M17
N14
N15
N16
N3,
M4
Symbol
TRST
TDO
TMS
TxSLEW_0
TxSLEW_1
TCK
TDI
Symbol
I, ST, ID
I, ST, IP
I, ST, IP
I, ST, IP
Type
O, TS
I, ST, ID
Type
1
1
Signal Description
Test Data Input.
Test data sampled with respect to the rising edge of TCK.
Test Data Output.
Test data driven with respect to the falling edge of TCK.
Test Mode Select.
Test Clock.
Clock input for JTAG test.
Test Reset.
Reset input for JTAG test.
Signal Description
Tx Output Slew Controls 0 and 1 Defaults.
These pins are read at startup or reset. Their value at
that time is used to set the default state of Register bits
27.11:10 for all ports. These register bits can be read
and overwritten after startup / reset.
These pins select the TX output slew rate for all ports
(rise and fall time) as follows:
TxSLEW_1
0
0
1
1
TxSLEW_0
2,3
0
1
0
1
2
Slew Rate (Rise and Fall
Time)
3.3 ns
3.6 ns
3.9 ns
4.2 ns
43