FWIXEPAD0SE001 INTEL [Intel Corporation], FWIXEPAD0SE001 Datasheet - Page 210
FWIXEPAD0SE001
Manufacturer Part Number
FWIXEPAD0SE001
Description
Advanced 8-Port 10/100 Mbps PHY Transceivers
Manufacturer
INTEL [Intel Corporation]
Datasheet
1.FWIXEPAD0SE001.pdf
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
212
Table 95. Interrupt Status Register (Address 19, Hex 13)
1. R = Read Only, LH = Latching High – cleared when read
2. The default values are updated on completion of reset and reflect the status or change in status at that
15:9
Bit
1:0
8
7
6
5
4
3
2
time. Intel recommends that the register status be read on completion of reset.
Name
Reserved
RxERCntFUL
ANDONE
SPEEDCHG
DUPLEXCHG
LINKCHG
Isolate
MDINT
Reserved
Description
RxER Counter Full Status.
0 = The internal counters have not reached maximum
1 = One of the internal counters has reached its maximum
Auto-Negotiation Status.
0 = Auto-negotiation has not completed
1 = Auto-negotiation has completed
Speed Change Status.
0 = A speed change has not occurred since last reading
1 = A speed change has occurred since last reading this
Duplex Change Status.
0 = A duplex change has not occurred since last reading this
register
1 = A duplex change has occurred since last reading this
register
Link Status Change Status.
0 = A link change has not occurred since last reading this
register
1 = A link change has occurred since last reading this
register
MII Isolate Change Status.
0 = An Isolate change has not occurred since last reading
1 = An Isolate change has occurred since last reading this
0 = Interrupt not pending
1 = Interrupt pending
Write as 0, ignore on Read
Reserved
values
value
this register
register
this register
register
Revision Date: August 28, 2003
Document Number: 249241
Revision Number: 007
Type
R/LH
R/LH
R/LH
R/LH
R/LH
R/LH
R/LH
R
R
1
Datasheet
Default
N/A
0
0
0
0
0
0
0
0
2
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