FWIXEPAD0SE001 INTEL [Intel Corporation], FWIXEPAD0SE001 Datasheet - Page 65

• Manufacturer Part Number: FWIXEPAD0SE001
• Description: Advanced 8-Port 10/100 Mbps PHY Transceivers
• Manufacturer: INTEL [Intel Corporation]

Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Table 21. Intel® LXT9785/LXT9785E SMII BGA23 Ball List in Alphanumeric Order by Ball
Location
Ball Signal
A10 MDIO1
A12 FIFOSEL0
A13 RxData4
A14 N/C
A15 FIFOSEL1
A16 N/C
A17 LINKHOLD
B10 MDC1
B12 CRS_DV4
B13 TxData5
B14 RxData5
B15 N/C
B16 CRS_DV6
A11 TxData4
B11 N/C
A1
A2
A3
A4
A5
A6
A7
A8
A9
B1
B2
B3
B4
B5
B6
B7
B8
B9
GNDD
VCCIO
RxData1
N/C
CRS_DV2
SYNC0
N/C
VCCIO
GNDD
N/C
N/C
GNDD
N/C
TxData2
RxData2
GNDD
CRS_DV3
N/C
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Type
–
–
O, TS
I, ID
O, TS, SL
I, ID
I, ID
–
–
I/O, TS, SL,
IP
I, ID
O, TS, SL,
ID, I, ST
O, TS
I, ID
O, TS, SL,
ID, I, ST
I, ID
O, TS, SL,
ID
O, TS
–
–
O, TS, ID
I, ID
O, TS
–
O, TS, SL
O, TS, ID
I, ST, ID
I, ID
O, TS, SL
I, ID
O, TS
O, TS, ID
O, TS, SL
1
Reference for
Full Description
Table 34 (page 95)
Table 34 (page 95)
Table 24 (page 82)
Table 24 (page 82)
Table 24 (page 82)
Table 24 (page 82)
Table 24 (page 82)
Table 34 (page 95)
Table 34 (page 95)
Table 28 (page 87)
Table 24 (page 82)
Table 24 (page 82)
Table 24 (page 82)
Table 24 (page 82)
Table 24 (page 82)
Table 24 (page 82)
Table 24 (page 82)
Table 24 (page 82)
Table 24 (page 82)
Table 34 (page 95)
Table 24 (page 82)
Table 24 (page 82)
Table 24 (page 82)
Table 34 (page 95)
Table 24 (page 82)
Table 24 (page 82)
Table 28 (page 87)
Table 24 (page 82)
Table 24 (page 82)
Table 24 (page 82)
Table 24 (page 82)
Table 24 (page 82)
Table 24 (page 82)
Ball Signal
B17 N/C
C10 N/C
C11 VCCIO
C12 N/C
C13 GNDD
C14 N/C
C15 RxData6
C16 SYNC1
C17 GNDD
D10 GNDD
D11 N/C
D12 CRS_DV5
D13 TxData6
D14 VCCIO
D15 GNDD
C1
C2
C3
C4
C5
C6
C7
C8
C9
D1
D2
D3
D4
D5
D6
D7
D8
D9
CRS_DV1
PREASEL
VCCIO
RxData0
TxData1
GNDD
N/C
N/C
N/C
MDINT1
GNDD
MDIX
GNDD
N/C
PAUSE
GNDD
TxData3
RxData3
Type
O, TS, ID
–
O, TS
I, ID
O, TS, SL
–
I, ID
O, TS, ID
O, TS, SL,
ID
OD, TS, SL,
IP
I, ID
–
O, TS,ID
–
I, ID
O, TS
I, ID
–
–
O, TS, SL,
ID, I, ST
–
I, ID
O, TS, SL,
ID, I, ST
–
O, TS, SL,
ID, I, ST
I, ID
O, TS
–
I, ID
O, TS, SL
I, ID
–
–
1
Reference for
Full Description
Table 24 (page 82)
Table 34 (page 95)
Table 24 (page 82)
Table 24 (page 82)
Table 24 (page 82)
Table 34 (page 95)
Table 24 (page 82)
Table 24 (page 82)
Table 24 (page 82)
Table 28 (page 87)
Table 24 (page 82)
Table 34 (page 95)
Table 24 (page 82)
Table 34 (page 95)
Table 24 (page 82)
Table 24 (page 82)
Table 24 (page 82)
Table 34 (page 95)
Table 34 (page 95)
Table 32 (page 90)
Table 34 (page 95)
Table 24 (page 82)
Table 32 (page 90)
Table 34 (page 95)
Table 24 (page 82)
Table 24 (page 82)
Table 24 (page 82)
Table 34 (page 95)
Table 24 (page 82)
Table 24 (page 82)
Table 24 (page 82)
Table 34 (page 95)
Table 34 (page 95)
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