FWIXEPAD0SE001 INTEL [Intel Corporation], FWIXEPAD0SE001 Datasheet - Page 199

• Manufacturer Part Number: FWIXEPAD0SE001
• Description: Advanced 8-Port 10/100 Mbps PHY Transceivers
• Manufacturer: INTEL [Intel Corporation]

Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Table 83. Control Register (Address 0) (Sheet 2 of 2)
Table 84. Status Register (Address 1)
1. R/W = Read/Write, SC = Self Clearing when operation complete.
2. During a hardware reset, all LHR information is latched in from the pins. During a software reset (0.15), the
3. LSHR = Default value is derived from a single device input pin state or a group of device input pin states as
4. Default value of Register bits 0.12, 0.13, and 0.8 are determined by the CFG pins as described in
5. Default value of Register bit 0.11 is determined by the LINKHOLD configuration pin.
1. R = Read Only
2. Bits that Latch High (LH) or Latch Low (LL) automatically clear when read.
Bit
5:0
Bit
15
14
13
12
11
10
9
8
7
6
7
6
LSHR information is not re-read from the pins. This information reverts back to the information that was
read in during the hardware reset. During a hardware rest, register information is unavailable from 1 ms
after de-assertion of the reset. During a software reset (0.15) the registers are available for reading. The
reset bit should be polled to see when the part has completed reset.
the pin(s) are latched at startup or hardware reset.
“Intel® LXT9785/9785E Global Hardware Configuration Settings” on page
Name
Collision Test
Speed Selection
1000 Mbps
Reserved
Name
100BASE-T4
100BASE-X
Full-Duplex
100BASE-X
Half-Duplex
10 Mbps Full-Duplex
10 Mbps Half-Duplex
100BASE-T2
Full-Duplex
100BASE-T2
Half-Duplex
Extended Status
Reserved
MF Preamble
Suppression
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Description
0 = PHY not able to perform 100BASE-T4
1 = PHY able to perform 100BASE-T4
0 = PHY not able to perform full-duplex 100BASE-X
1 = PHY able to perform full-duplex 100BASE-X
0 = PHY not able to perform half-duplex 100BASE-X
1 = PHY able to perform half-duplex 100BASE-X
0 = PHY not able to operate at 10 Mbps in full-duplex
1 = PHY able to operate at 10 Mbps in full-duplex
0 = PHY not able to operate at 10 Mbps in half-duplex
1 = PHY able to operate at 10 Mbps in half-duplex
0 = PHY not able to perform full-duplex 100BASE-T2
1 = PHY able to perform full-duplex 100BASE-T2
0 = PHY not able to perform half-duplex 100BASE-T2
1 = PHY able to perform half-duplex 100BASE-T2
0 = No extended status information in Register 15
1 = Extended status information in Register 15
Write as 0, ignore on Read
0 = PHY will not accept management frames with
1 = PHY accepts management frames with preamble
Description
This bit is ignored by the LXT9785/LXT9785E
0 = Disable COL signal test
1 = Enable COL signal test
Write as 0, ignore on Read
0.6
1
1
0
0
mode
mode
mode
preamble suppressed
suppressed
0.13
1 = Reserved
0 = 1000 Mbps (not allowed)
1 = 100 Mbps
0 = 10 Mbps
129.
Type
R/W
R/W
R/W
Type
R
R
R
R
R
R
R
R
R
R
1
1,2
Table 42,
Default
000000
Default
0
0
0
1
1
1
1
0
0
0
0
0
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