FWIXEPAD0SE001 INTEL [Intel Corporation], FWIXEPAD0SE001 Datasheet - Page 209

• Manufacturer Part Number: FWIXEPAD0SE001
• Description: Advanced 8-Port 10/100 Mbps PHY Transceivers
• Manufacturer: INTEL [Intel Corporation]

Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Table 94. Interrupt Enable Register (Address 18, Hex 12)
1. R/W = Read/Write
2. In 10 Mbps operation, Register bit 18.13 = 1 cannot be used when Register bits 18.15:14 = “11” and in
3. SFD Frame Alignment is applicable to SMII and SS-SMII only.
5. Default values are set by hardware configuration pins FIFOSEL1 and FIFOSEL0 (see
4. LSHR = Default value is derived from a single device input pin state or a group of device input pin states as
15:14
12:9
RMII mode, Registers bits 18.15:14 = “11” or “10” cannot be used because the minimum Inter Gap Packet
becomes less than specified in the *IEEE 802.3 specification.
the pin(s) are latched at startup or hardware reset
LXT9785/LXT9785E Receive FIFO Depth Considerations” on page
Bit
13
8
7
6
5
4
3
2
1
0
2
Name
RxFIFO Initial
Fill
SFD Frame
Alignment
(RxDV asserts
with CRS when
enabled)
Reserved
CNTRMSK
ANMSK
SPEEDMSK
DUPLEXMSK
LINKMSK
ISOLMSK
Reserved
INTEN
TINT
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
3
Description
00 = Reserved
01 = Low, 16 bits
10 = Normal, 32 bits (default)
11 = Jumbo packets, 128 bits
10 Mbps
100 Mbps
Write as 0, ignore on Read
Mask for Counter Full
0 = Do not allow event to cause interrupt
1 = Enable event to cause interrupt
Mask for Auto-Negotiate Complete
0 = Do not allow event to cause interrupt
1 = Enable event to cause interrupt
Mask for Speed Interrupt
0 = Do not allow event to cause interrupt
1 = Enable event to cause interrupt
Mask for Duplex Interrupt
0 = Do not allow event to cause interrupt
1 = Enable event to cause interrupt
Mask for Link Status Interrupt
0 = Do not allow event to cause interrupt
1 = Enable event to cause interrupt
Mask for Isolate Interrupt
0 = Do not allow event to cause interrupt
1 = Enable event to cause interrupt
Write as 0, ignore on Read
0 = Disable interrupts on this port
1 = Enable interrupts on this port
0 = Normal operation
1 = Test force interrupt on MDINT
When Register bit 16.5 = 1, preamble is
not suppressed.
When Register bit 16.5 = 0, SFD is always
aligned, and preamble is suppressed.
When enabled, all but one byte of
preamble is suppressed.
0 = Disabled
1 = Enabled
0 = Disabled
1 = Enabled
50).
Table 17, “Intel®
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
LSHR
Default
0000
0
0
0
0
0
0
0
0
0
0
0
211
4,5