FWIXEPAD0SE001 INTEL [Intel Corporation], FWIXEPAD0SE001 Datasheet - Page 90

• Manufacturer Part Number: FWIXEPAD0SE001
• Description: Advanced 8-Port 10/100 Mbps PHY Transceivers
• Manufacturer: INTEL [Intel Corporation]

LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
92
Table 32. Intel
1. Type Column Coding: I = Input, O = Output, OD = Open Drain Output, ST = Schmitt Triggered Input, TS =
2. The IP/ID resistors are disabled during hardware power-down mode.
BGA23
M14
L2,
L3,
M1
D2
Three-State-able Output, SL = Slew-rate Limited Output, IP = Weak Internal Pull-Up, ID = Weak Internal
Pull-Down.
Designation
®
Ball/Pin
LXT9785/LXT9785E Miscellaneous Signal Descriptions – BGA23 (Sheet 3 of 4)
PQFP
173
59
85
86
87
G_FX/TP
Symbol
CFG_3
CFG_2
CFG_1
MDIX
I, ID, ST
I, ST, ID
I, ST, ID
Type
1
Signal Description
MDIX Select Default.
This pin is read at startup or reset. Its value at that time
is used to set the default state of Register bit 27.8 for
all ports. These register bits can be read and
overwritten after startup / reset. Refer to
“Intel® LXT9785/LXT9785E MDIX Selection” on
page
When AMDIX_EN is active this pin is ignored.
When AMDIX_EN is inactive, all ports are forced to the
MDI or the MDIX function regardless of segmentation.
If this pin is active (high), MDI crossover (MDIX) is
selected. If this pin is inactive, non-crossover MDI
mode is set.
This pin is shared with RMII-RxER0. An external pull-
up resistor (see applications section for value) can be
used to set MDIX active while RxER0 is three-stated
during H/W reset. If no pull-up is used, the default
MDIX state is set inactive via the internal pull-down
resistor. Do not tie this pin directly to VCCIO (vs. using
a pull-up) in non-RMII modes.
Global Port Configuration Defaults 1-3.
These pins are read at startup or reset. Their value at
that time is used to set the default state of register bits
shown in
Hardware Configuration Settings” on page 129
ports. These register bits can be read and overwritten
after startup / reset.
When operating in Hardware Control Mode, these pins
provide configuration control options for all the ports
(refer to
Hardware Configuration Settings” on page 129
details).
Global FX/TP Enable Default.
This pin is read at startup or reset. Its value at that time
is used to set the default state of Register bit 16.0 for
all ports. These register bits can be read and
overwritten after startup / reset. Refer to
Configuration Register (Address 16, Hex 10)” on page
This input selects whether all the ports are defaulted to
TP vs. FX mode.
119.
Table 42 “Intel® LXT9785/9785E Global
Table 42 “Intel® LXT9785/9785E Global
2
Revision Date: August 28, 2003
Document Number: 249241
Revision Number: 007
Table 92 “Port
Table 40
Datasheet
for all
for
207.