FWIXEPAD0SE001 INTEL [Intel Corporation], FWIXEPAD0SE001 Datasheet - Page 197

• Manufacturer Part Number: FWIXEPAD0SE001
• Description: Advanced 8-Port 10/100 Mbps PHY Transceivers
• Manufacturer: INTEL [Intel Corporation]

7.0
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Table 82. Intel
Register Definitions
The LXT9785/LXT9785E register set includes multiple 16-bit registers, 18 registers per port.
Table 82
through
individual registers and
provides a consolidated memory map of all registers.
Base registers (0 through 8) are defined in accordance with the “Reconciliation Sublayer and
Media Independent Interface” and “Physical Layer Link Signaling for 10/100 Mbps Auto-
Negotiation” sections of the IEEE 802.3 standard.
Additional registers (16 through 21, 25, 27, and 29) are defined in accordance with the IEEE 802.3
standard for adding unique chip functions.
The BGA15 package on some registers has different default values. Some LXT9785 features are
not available on the BGA15 package. These differences are called out in the register description
and in the table notes in individual register tables.
Address
22-24
10
15
16
17
18
19
20
21
25
26
0
1
2
3
4
5
6
7
8
9
®
LXT9785/LXT9785E Register Set (Sheet 1 of 2)
Table 100, “Cable Diagnostics Register (Address 29, Hex 1D)” on page 217
presents a complete register listing.
Register Name
“Control Register (Address 0)”
“Status Register (Address 1)”
“PHY Identification Register 1 (Address 2)”
“PHY Identification Register 2 (Address 3)”
“Auto-Negotiation Advertisement Register (Address 4)”
“Auto-Negotiation Link Partner Base Page Ability Register
(Address 5)”
“Auto-Negotiation Expansion Register (Address 6)”
“Auto-Negotiation Next Page Transmit Register (Address 7)”
“Auto-Negotiation Link Partner Next Page Receive Register
(Address 8)”
1000BASE-T/100BASE-T2 Control
1000BASE-T/100BASE-T2 Status
Extended Status
“Port Configuration Register (Address 16, Hex 10)”
“Quick Status Register (Address 17, Hex 11)”
“Interrupt Enable Register (Address 18, Hex 12)”
“Interrupt Status Register (Address 19, Hex 13)”
“LED Configuration Register (Address 20, Hex 14)”
“Receive Error Count Register (Address 21, Hex 15)”
Reserved
“RMII Out-of-Band Signaling Register (Address 25, Hex 19)”
Reserved
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 101, “Intel® LXT9785/LXT9785E Register Bit Map” on page 219
Table 83, “Control Register (Address 0)” on page 200
Bit Assignments
Refer to
Refer to
Refer to
Refer to
Refer to
Refer to
Refer to
Refer to
Refer to
Not Implemented
Not Implemented
Not Implemented
Refer to
Refer to
Refer to
Refer to
Refer to
Refer to
N/A
Refer to
N/A
Table 83 on page 200
Table 84 on page 201
Table 85 on page 203
Table 86 on page 203
Table 87 on page 204
Table 88 on page 205
Table 89 on page 206
Table 90 on page 206
Table 91 on page 207
Table 92 on page 207
Table 93 on page 209
Table 94 on page 211
Table 95 on page 212
Table 96 on page 213
Table 97 on page 214
Table 98 on page 215
define
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