FWIXEPAD0SE001 INTEL [Intel Corporation], FWIXEPAD0SE001 Datasheet - Page 123

• Manufacturer Part Number: FWIXEPAD0SE001
• Description: Advanced 8-Port 10/100 Mbps PHY Transceivers
• Manufacturer: INTEL [Intel Corporation]

4.4
4.4.1
4.4.2
4.4.2.1
4.4.2.2
4.4.2.3
4.4.2.4
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Operating Requirements
Power Requirements
The LXT9785/LXT9785E requires four power supply inputs: VCCD, VCCA, VCCPECL and
VCCIO. The digital and analog circuits require 2.5 V supplies (VCCD, VCCR, and VCCT). These
inputs may be supplied from a single source although decoupling is required to each respective
ground. The fiber VCCPECL supply can be connected to either 2.5 V or 3.3 V.
A separate power supply may be used for the MII, JTAG and MDIO (VCCIO) interfaces. The
power supply may be either +2.5 V or +3.3 V. VCCIO should be supplied from the same power
source used to supply the controller on the other side of the interface. Refer to
LXT9785/LXT9785E Digital I/O DC Electrical Characteristics (VCCIO = 2.5 V +/- 5%)” on
page 174, Table 54, “Intel® LXT9785/LXT9785E Digital I/O DC Electrical Characteristics
(VCCIO = 3.3 V +/- 5%)” on page 175,
DC Electrical Characteristics – SD Pins” on page 175
As a matter of good practice, these supplies should be as clean as possible. Typical filtering and
decoupling are shown in
to the same time as possible. However, there are no specific timing requirements.
Clock/SYNC Requirements
Reference Clock
The LXT9785/LXT9785E requires a constant enabled reference clock (REFCLK). REFCLK’s
frequency must be 50 MHz for RMII or 125 MHz for SMII/SS-SMII. The reference clock is used
to generate transmit signals and recover receive signals. A crystal-based clock is recommended
over a derived clock (that is, PLL-based) to minimize transmit jitter. Refer to
LXT9785/LXT9785E Required Clock Characteristics” on page 175
For applications that use a single 8-port sectionalization, REFCLK0 and REFCLK1 must always
be tied together and to the source. In 2x4 applications, REFCLK0 and REFCLK1 are not tied
together.
TxCLK Signal (SS-SMII only)
The LXT9785/LXT9785E requires a 125 MHz input transmit clock synchronous with TxDatan
and frequency locked to REFCLK. See
TxSYNC Signal (SMII/SS-SMII)
The LXT9785/LXT9785E requires a 12.5 MHz input pulse for SMII synchronization. See
Figure 22 on page 141.
RxSYNC Signal (SS-SMII only)
The LXT9785/LXT9785E provides a 12.5 MHz output pulse synchronous with the RxDatan
outputs. See
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 23 on page 141.
Figure 34 on page
Figure 22 on page 141.
and
168. The power supplies should be brought up as close
Table 55, “Intel® LXT9785/LXT9785E Digital I/O
for I/O characteristics.
for clock timing requirements.
Table 56, “Intel®
Table 53, “Intel®
125