FWIXEPAD0SE001 INTEL [Intel Corporation], FWIXEPAD0SE001 Datasheet - Page 148

• Manufacturer Part Number: FWIXEPAD0SE001
• Description: Advanced 8-Port 10/100 Mbps PHY Transceivers
• Manufacturer: INTEL [Intel Corporation]

LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
4.10
4.10.1
150
Note: The LXT9785/LXT9785E does not support fiber connections at 10 Mbps.
The far-end fault detection process in fiber operation requires idles to establish link. Link will not
establish if a far-end fault pattern is the initial signal detected.
Either fault condition causes the LXT9785/LXT9785E to drop the link unless Forced Link Pass is
selected (16.14 = 1). Link down condition is then reported via interrupts and status bits.
In response to locally detected signal faults (SD activated by the local fiber transceiver), the
affected port can transmit the far end fault code if fault code transmission is enabled by Register bit
16.2.
The occurrence of a Far End Fault causes all transmission of data from the Reconciliation Sublayer
to stop and the Far End fault code to begin. The Far End Fault code consists of 84 ones’s followed
by a single “0” and is repeated until the Far End Fault condition is removed.
10 Mbps Operation
The LXT9785/LXT9785E operates as a standard 10BASE-T transceiver and supports all the
standard 10 Mbps functions. During 10BASE-T (10T) operation, the LXT9785/LXT9785E
transmits and receives Manchester-encoded data across the network link. When the MAC is not
actively transmitting data, the device sends out link pulses on the line.
In 10T mode, the polynomial scrambler/descrambler is inactive. Manchester-encoded signals
received from the network are decoded by the LXT9785/LXT9785E and sent across the MII to the
MAC.
Preamble Handling
The LXT9785/9785E offers two options for preamble handling, which are selected by Register bit
16.5. In 10BASE-T mode, when Register bit 16.5 = 0, the device strips the preamble off the
received packets. In RMII and the SMII modes, the CRS signal is asserted based upon receive
activity. In the SMII modes, Out-of-Band (OOB) signaling is present until the SFD is output. The
DV signal is initially asserted in the frame that the SFD is output. In RMII mode, zeros are output
after receive activity is detected until the SFD is output. The packet is output following the SFD.
When Register bit 16.5 = 1 in 10BASE-T mode, the LXT9785/LXT9785E passes the preamble
through the RMII and the SMII interfaces. In RMII and the SMII modes, the CRS signal is asserted
based upon receive activity. In the SMII modes, OOB signaling is continued until preamble is
available from the receive FIFO. After the preamble, the SFD is output with the initial assertion of
the DV signal. The RMII interface outputs zeros after receive activity is detected until preamble is
available from the FIFO. The number of zero nibbles output before preamble is based upon the
FIFO initial fill settings (Register bits 18.15:14). The preamble is followed by the SFD and the
packet body. Register bit 16.5 has no effect in 100 Mbps operation.
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When Register bit 16.2 = 1, transmission of the far end fault code is enabled. The LXT9785/
LXT9785E transmits far end fault code if fault conditions are detected by the Signal Detect
pins.
When Register bit 16.2 = 0, the LXT9785/LXT9785E does not transmit far end fault code. It
continues to transmit idle code and may or may not drop link depending on the setting for
Register bit 16.14.
Revision Date: August 28, 2003
Document Number: 249241
Revision Number: 007
Datasheet