ISP1362EE/01 PHILIPS [NXP Semiconductors], ISP1362EE/01 Datasheet - Page 15

• Manufacturer Part Number: ISP1362EE/01
• Description: Single-chip Universal Serial Bus On-The-Go controller
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
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Product data
9.1.1 Memory organization for the HC
9.1 Memory organization
The buffer memory in the HC uses a multiconfigurable direct addressing architecture.
The 4096 bytes HC buffer memory is shared by the ISTL0, ISTL1, INTL and ATL
buffers. ISTL0 and ISTL1 are used for isochronous traffic (double buffer), INTL is
used for interrupt traffic, and ATL is used for control and bulk traffic.
The allocation of the buffer memory follows the sequence ISTL0, ISTL1, INTL, ATL
and unused memory. For example, consider that the buffer sizes of the ISTL, INTL
and ATL buffers are 1024 bytes, 1024 bytes and 1024 bytes, respectively. Then,
ISTL0 will start from memory location 0, ISTL1 will start from memory location 1024
(size of ISTL0), INTL will start from memory location 2048 (size of ISTL0 + size of
ISTL1) and ATL will start from memory location 3072 (size of ISTL0 + size of
ISTL1 + size of INTL).
The HCD has the responsibility to ensure that the sum of the four memory buffers
does not exceed the total memory size. If this condition is violated, it will lead to data
corruption. The buffer size must be a multiple of two bytes (one word).
The buffer memory of the DC follows a similar architecture. Details on the DC
memory area allocation can be found in
memory does not support the direct addressing mode.
The HC in the ISP1362 has a total of 4096 bytes of buffer memory. This buffer area is
divided into four parts (see
Table 4:
The ISTL0 and ISTL1 buffers must have the same size. Memory is allocated by
the HC according to the value set by the HCD in HcISTLBufferSize,
HcINTLBufferSize and HcATLBufferSize. All buffer sizes must be multiples of two
bytes (one word).
Buffer memory area
ISTL0 and ISTL1
INTL
ATL
Buffer memory areas and their applications
Rev. 03 — 06 January 2004
Table 4
and
Figure
Section
Application
isochronous transfer (double buffering)
interrupt transfer
control and bulk transfer
4):
13.3. Note that the DC buffer
Single-chip USB OTG controller
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