ISP1362EE/01 PHILIPS [NXP Semiconductors], ISP1362EE/01 Datasheet - Page 56

• Manufacturer Part Number: ISP1362EE/01
• Description: Single-chip Universal Serial Bus On-The-Go controller
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
9397 750 12337
Product data
The DMA subsystem of an IBM-compatible PC is based on the Intel 8237 DMA
controller. It operates as a ‘fly-by’ DMA controller. Data is not stored in the DMA
controller, but it is transferred between an I/O port and a memory address. A typical
example of the DC in 8237 compatible DMA mode is given in
The 8237 has two control signals for each DMA channel: DREQ (DMA Request) and
DACK (DMA Acknowledge). General control signals are HRQ (Hold Request) and
HLDA (Hold Acknowledge). The bus operation is controlled by MEMR (Memory
Read), MEMW (Memory Write), IOR (I/O read) and IOW (I/O write).
The following example shows the steps that occur in a typical DMA transfer:
10. The 8237 deasserts the DACK output indicating that the DC must stop placing
1. The DC receives a data packet in one of its endpoint buffer memory. The packet
2. The DC asserts the DREQ2 signal requesting the 8237 for a DMA transfer.
3. The 8237 asks the CPU to release the bus by asserting the HRQ signal.
4. After completing the current instruction cycle, the CPU places the bus control
5. The 8237 now sets its address lines to 1234H and activates the MEMW and IOR
6. The 8237 asserts DACK to inform the DC that it will start a DMA transfer.
7. The DC now places the word to be transferred on the data bus lines because its
8. The 8237 waits one DMA clock period and then deasserts MEMW and IOR. This
9. The DC deasserts the DREQ2 signal to indicate to the 8237 that DMA is no
Fig 26. DC in 8327 compatible DMA mode.
must be transferred to memory address 1234H.
signals (MEMR, MEMW, IOR and IOW) and the address lines in three-state and
asserts HLDA to inform the 8237 that it has control of the bus.
control signals.
RD signal was asserted by the 8237.
latches and stores the word at the desired memory location. It also informs
the DC that the data on the bus lines has been transferred.
longer needed. In the Single cycle mode, this is done after each byte or word; in
the Burst mode, following the last transferred byte or word of the DMA cycle.
data on the bus.
ISP1362
Rev. 03 — 06 January 2004
D0 to D15
DREQ2
DACK2
WR
RD
RAM
MEMR
MEMW
DREQ
DACK
IOR
IOW
CONTROLLER
DMA
8237
Single-chip USB OTG controller
HLDA
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
HRQ
Figure
HRQ
HLDA
ISP1362
CPU
26.
004aaa047
56 of 150