LPC47M172_07 SMSC [SMSC Corporation], LPC47M172_07 Datasheet - Page 115

• Manufacturer Part Number: LPC47M172_07
• Description: Advanced I/O Controller with Motherboard GLUE Logic
• Manufacturer: SMSC [SMSC Corporation]

7.25.2 Keyboard Data Write
7.25.3 Keyboard Data Read
7.25.4 Keyboard Command Write
7.25.5 Keyboard Status Read
7.25.6 CPU-to-Host Communication
7.25.7 Host-to-CPU Communication
7.25.8 KIRQ
SMSC LPC47M172
This is an 8 bit write only register. When written, the C/D status bit of the status register is cleared to zero
and the IBF bit is set.
This is an 8 bit read only register. If enabled by “ENABLE FLAGS”, when read, the KIRQ output is cleared
and the OBF flag in the status register is cleared. If not enabled, the KIRQ and/or AUXOBF1 must be
cleared in software.
This is an 8 bit write only register. When written, the C/D status bit of the status register is set to one and
the IBF bit is set.
This is an 8 bit read only register. Refer to the description of the Status Register for more information.
The LPC47M172 CPU can write to the Output Data register via register DBB. A write to this register
automatically sets Bit 0 (OBF) in the Status register. See Table 7.11.
The host system can send both commands and data to the Input Data register. The CPU differentiates
between commands and data by reading the value of Bit 3 of the Status register. When bit 3 is “1”, the
CPU interprets the register contents as a command. When bit 3 is “0”, the CPU interprets the register
contents as data. During a host write operation, bit 3 is set to “1” if SA2 = 1 or reset to “0” if SA2 = 0.
If “EN FLAGS” has been executed and P24 is set to a one: the OBF flag is gated onto KIRQ. The KIRQ
signal can be connected to system interrupt to signify that the LPC47M172 CPU has written to the output
data register via “OUT DBB,A”. If P24 is set to a zero, KIRQ is forced low. On power-up, after a valid RST
pulse has been delivered to the device, KIRQ is reset to 0. KIRQ will normally reflects the status of writes
“DBB”. (KIRQ is normally selected as IRQ1 for keyboard support.)
If “EN FLAGS” has not been executed: KIRQ can be controlled by writing to P24. Writing a zero to P24
forces KIRQ low; a high forces KIRQ high.
OUT DBB
8042 INSTRUCTION
Set OBF, and, if enabled, the KIRQ output signal goes high
Table 7.11 - Host Interface Flags
DATASHEET
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FLAG
Advanced I/O Controller with Motherboard GLUE Logic
SMSC/Non-SMSC Register Sets (Rev. 01-11-07)
Datasheet