LPC47M172_07 SMSC [SMSC Corporation], LPC47M172_07 Datasheet - Page 98

• Manufacturer Part Number: LPC47M172_07
• Description: Advanced I/O Controller with Motherboard GLUE Logic
• Manufacturer: SMSC [SMSC Corporation]

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Note 1:
Note 2:
Note 3:
7.11
7.11.1 Description
SMSC/Non-SMSC Register Sets (Rev. 01-11-07)
data
ecpAFifo
dsr
dcr
cFifo
ecpDFifo
tFifo
cnfgA
cnfgB
ecr
Reference Document: IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev
1.14, July 14, 1993. This document is available from Microsoft.
The bit map of the Extended Parallel Port registers is:
These registers are available in all modes.
All FIFOs use one common 16 byte FIFO.
The ECP Parallel Port Config Reg B reflects the IRQ and DMA channel selected by the Configuration
Registers.
ECP Implementation Standard
This specification describes the standard interface to the Extended Capabilities Port (ECP). All LPC
devices supporting ECP must meet the requirements contained in this section or the port will not be
supported by Microsoft. For a description of the ECP Protocol, please refer to the IEEE 1284 Extended
Capabilities Port Protocol and ISA Interface Standard, Rev. 1.14, July 14, 1993. This document is
available from Microsoft.
The port is software and hardware compatible with existing parallel ports so that it may be used as a
standard LPT port if ECP is not required. The port is designed to be simple and requires a small number of
gates to implement. It does not do any “protocol” negotiation, rather it provides an automatic high
burst-bandwidth channel that supports DMA for ECP in both the forward and reverse directions.
Small FIFOs are employed in both forward and reverse directions to smooth data flow and improve the
maximum bandwidth requirement. The size of the FIFO is 16 bytes deep. The port supports an automatic
handshake for the standard parallel port to improve compatibility mode transfer speed.
The port also supports run length encoded (RLE) decompression (required) in hardware. Compression is
accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the
nReverseRequest, nInit
nAckReverse, PError
Xflag, Select
ECPMode, nSelectln
HostClk, nStrobe
Addr/RLE
compress intrValue
nBusy
PD7
D7
0
0
MODE
nAck
PD6
D6
0
0
Direction
PError
PD5
D5
DATASHEET
0
Parallel Port IRQ
Parallel Port Data FIFO
ECP Data FIFO
nErrIntrE
ackIntEn
Select
PD4
Test FIFO
Address or RLE field
Page 98
D4
1
n
dmaEn serviceIntr
SelectI
nFault
PD3
D3
n
0
PD2
nInit
D2
0
0
Parallel Port DMA
autofd
PD1
D1
full
0
0
strobe
empty
PD0
D0
0
0
SMSC LPC47M172
NOTE
2
1
1
2
2
2