LPC47M172_07 SMSC [SMSC Corporation], LPC47M172_07 Datasheet - Page 76

• Manufacturer Part Number: LPC47M172_07
• Description: Advanced I/O Controller with Motherboard GLUE Logic
• Manufacturer: SMSC [SMSC Corporation]

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Bit 3
Bits 4 through 7
6.28.5 FIFO Control Register (FCR)
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4,5
Bit 6,7
6.28.6 Interrupt Identification Register (IIR)
SMSC/Non-SMSC Register Sets (Rev. 01-11-07)
This bit enables the MODEM Status Interrupt when set to logic “1”. This is caused when one of the
Modem Status Register bits changes state.
These bits are always logic “0”.
Address Offset = 2H, DLAB = X, WRITE
This is a write only register at the same location as the IIR. This register is used to enable and clear the
FIFOs, set the RCVR FIFO trigger level. Note: DMA is not supported. The UART is shadowed in the
UART1 FIFO Control Shadow Register (Power Control/Runtime Register at offset 0x1A).
Setting this bit to a logic “1” enables both the XMIT and RCVR FIFOs.
disables both the XMIT and RCVR FIFOs and clears all bytes from both FIFOs. When changing from FIFO
Mode to non-FIFO (16450) mode, data is automatically cleared from the FIFOs. This bit must be a 1 when
other bits in this register are written to or they will not be properly programmed.
Setting this bit to a logic “1” clears all bytes in the RCVR FIFO and resets its counter logic to 0. The shift
register is not cleared. This bit is self-clearing.
Setting this bit to a logic “1” clears all bytes in the XMIT FIFO and resets its counter logic to 0. The shift
register is not cleared. This bit is self-clearing.
Writing to this bit has no effect on the operation of the UART. The RXRDY and TXRDY pins are not
available on this chip.
Reserved
These bits are used to set the trigger level for the RCVR FIFO interrupt.
Address Offset = 2H, DLAB = X, READ
By accessing this register, the host CPU can determine the highest priority interrupt and its source. Four
levels of priority interrupt exist. They are in descending order of priority:
1.
2.
3.
4.
Receiver Line Status (highest priority)
Received Data Ready
Transmitter Holding Register Empty
MODEM Status (lowest priority)
DATASHEET
Page 76
Clearing this bit to a logic “0”
SMSC LPC47M172