LPC47M172_07 SMSC [SMSC Corporation], LPC47M172_07 Datasheet - Page 157
LPC47M172_07
Manufacturer Part Number
LPC47M172_07
Description
Advanced I/O Controller with Motherboard GLUE Logic
Manufacturer
SMSC [SMSC Corporation]
Datasheet
1.LPC47M172_07.pdf
(226 pages)
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Chapter 9
SMSC LPC47M172
REGISTER
OFFSET
0D-14
17-1F
(hex)
0C
00
01
02
03
04
05
06
07
08
09
0A
0B
15
16
Table 9.1 shows the runtime registers summary in the GPIO logical Device. Table 9.2 shows the runtime
registers description in the GPIO logical device. These registers can only be accessed when LD_NUM bit
in the TEST 7 configuration register is ‘0’ (see Table 11.3). The register offsets are from the base address
programmed in the GPIO logical device.
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
PCI Reset
GPIO Runtime Registers
Table 9.1 - GPIO Runtime Registers Summary, LD_NUM = 0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VCC POR
DATASHEET
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VTR POR
Page 157
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x04
0x04
0x04
0x04
0x05
0x00
0x00
-
-
RESET
SOFT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Advanced I/O Controller with Motherboard GLUE Logic
SMSC/Non-SMSC Register Sets (Rev. 01-11-07)
REGISTER
GP10
GP11
GP12
GP13
GP14
GP15
GP16
GP17
GP20
GP21
GP22
GP23
GP24
Reserved – reads return 0
GP1
GP2
Reserved – reads return 0
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