LPC47M172_07 SMSC [SMSC Corporation], LPC47M172_07 Datasheet - Page 45

• Manufacturer Part Number: LPC47M172_07
• Description: Advanced I/O Controller with Motherboard GLUE Logic
• Manufacturer: SMSC [SMSC Corporation]

6.4.8
BIT 0 – 1 DRV x BUSY
BIT 4 COMMAND BUSY
BIT 5 NON-DMA
BIT 6 DIO
BIT 7 RQM
SMSC/Non-SMSC Register Sets (Rev. 01-11-07)
Main Status Register
Address 3F4 READ ONLY
The Main Status Register is a read-only register and indicates the status of the disk controller. The Main
Status Register can be read at any time. The MSR indicates when the disk controller is ready to receive
data via the Data Register. It should be read before each byte transferring to or from the data register
except in DMA mode. No delay is required when reading the MSR after a data transfer.
These bits are set to 1s when a drive is in the seek portion of a command, including implied and
overlapped seeks and recalibrates.
This bit is set to a 1 when a command is in progress. This bit will go active after the command byte has
been accepted and goes inactive at the end of the results phase. If there is no result phase (Seek,
Recalibrate commands), this bit is returned to a 0 after the last command byte.
Reserved, read ‘0’. This part does not support non-DMA mode.
Indicates the direction of a data transfer once a RQM is set. A 1 indicates a read and a 0 indicates a write
is required.
Indicates that the host can transfer data if set to a 1. No access is permitted if set to a 0.
DT1
RQM
0
1
0
1
7
DT0
0
0
1
1
DIO
6
DRATE0
DRATE0
DRATE0
DRATE1
Table 6.10 - Default Precompensation Delays
DRVDEN1 (1)
Table 6.9 - DRVDEN Mapping
DATA RATE
NON
DMA
500 Kbps
300 Kbps
250 Kbps
5
2 Mbps
1 Mbps
DATASHEET
BUSY
CMD
4
DRATE1
nDENSEL
DRATE0
DENSEL
Page 45
DRVDEN0 (1)
PRECOMPENSATION
Reserved Reserved
3
DELAYS
41.67 ns
20.8 ns
125 ns
125 ns
125 ns
2/1 MB 5.25” FDDS
2/1.6/1 MB 3.5” (3-MODE)
PS/2
4/2/1 MB 3.5”
2
Advanced I/O Controller with Motherboard GLUE Logic
DRIVE TYPE
BUSY
DRV1
1
DRV0
BUSY
0
SMSC LPC47M172
Datasheet