LPC47M172_07 SMSC [SMSC Corporation], LPC47M172_07 Datasheet - Page 86

• Manufacturer Part Number: LPC47M172_07
• Description: Advanced I/O Controller with Motherboard GLUE Logic
• Manufacturer: SMSC [SMSC Corporation]

REGISTER
ADDRESS
ADDR = 0
ADDR = 0
ADDR = 1
ADDR = 2
ADDR = 2
ADDR = 3
ADDR = 4
ADDR = 5
ADDR = 6
ADDR = 7
ADDR = 0
ADDR = 1
DLAB = 0
DLAB = 0
DLAB = 0
DLAB = 1
DLAB = 1
(Note 1)
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
SMSC/Non-SMSC Register Sets (Rev. 01-11-07)
Receive Buffer Register (Read Only)
Transmitter Holding Register (Write Only)
Interrupt Enable Register
Interrupt Ident. Register (Read Only)
FIFO Control Register (Write Only)
Line Control Register
MODEM Control Register
Line Status Register
MODEM Status Register
Scratch Register (Note 5)
Divisor Latch (LS)
Divisor Latch (MS)
REGISTER NAME
Table 32 - Register Summary for an Individual UART Channel
REGISTER
FCR
SYMBOL
RBR
MCR
MSR
SCR
DLM
THR
LCR
LSR
DDL
IER
IIR
(Note 8)
Page 86
Data Bit 0
(Note 2)
Data Bit 0
Enable
Received
Data
Available
Interrupt
(ERDAI)
“0” if Interrupt
Pending
FIFO Enable
Word Length
Select Bit 0
(WLS0)
Data Terminal
Ready (DTR)
Data Ready
(DR)
Delta Clear to
Send (DCTS)
Bit 0
Bit 0
Bit 8
BIT 0
DATASHEET
Data Bit 1
Data Bit 1
Enable
Transmitter
Holding
Register
Empty
Interrupt
(ETHREI)
Interrupt ID
Bit
RCVR FIFO
Reset
Word Length
Select Bit 1
(WLS1)
Request to
Send (RTS)
Overrun
Error (OE)
Delta Data
Set Ready
(DDSR)
Bit 1
Bit 1
Bit 9
BIT 1
Data Bit 2
Data Bit 2
Enable
Receiver
Line Status
Interrupt
(ELSI)
Interrupt ID
Bit
XMIT FIFO
Reset
Number of
Stop Bits
(STB)
OUT1
(Note 4)
Parity Error
(PE)
Trailing
Edge Ring
Indicator
(TERI)
Bit 2
Bit 2
Bit 10
BIT 2
SMSC LPC47M172
Data Bit 3
Data Bit 3
Enable
MODEM
Status
Interrupt
(EMSI)
Interrupt ID
Bit
DMA Mode
Select
(Note 7)
Parity
Enable
(PEN)
OUT2
(Note 4)
Framing
Error (FE)
Delta Data
Carrier
Detect
(DDCD)
Bit 3
Bit 3
Bit 11
BIT 3
(Note 6)
Data Bit 4
Data Bit 4
0
0
Reserved
Even Parity
Select
(EPS)
Loop
Break
Interrupt
(BI)
Clear to
Send (CTS)
Bit 4
Bit 4
Bit 12
BIT 4
Data Bit 5
Data Bit 5
0
0
Reserved
Stick Parity
0
Transmitter
Holding
Register
(THRE)
Data Set
Ready
(DSR)
Bit 5
Bit 5
Bit 13
BIT 5
Data Bit 6
Data Bit 6
0
FIFOs
Enabled
(Note 6)
RCVR Trigger
LSB
Set Break
0
Transmitter
Empty
(TEMT)
(Note 3)
Ring Indicator
(RI)
Bit 6
Bit 6
Bit 14
BIT 6
Data Bit 7
Data Bit 7
0
FIFOs
Enabled
(Note 6)
RCVR
Trigger
MSB
Divisor
Latch
Access Bit
(DLAB)
0
Error in
RCVR
FIFO
(Note 6)
Data
Carrier
Detect
(DCD)
Bit 7
Bit 7
Bit 15
BIT 7