LPC47M172_07 SMSC [SMSC Corporation], LPC47M172_07 Datasheet - Page 116

• Manufacturer Part Number: LPC47M172_07
• Description: Advanced I/O Controller with Motherboard GLUE Logic
• Manufacturer: SMSC [SMSC Corporation]

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
7.25.9 MIRQ
7.25.10 External Keyboard and Mouse Interface
Note:
7.25.11 Keyboard Power Management
7.25.12 Soft Power Down Mode
7.25.13 Hard Power Down Mode
SMSC/Non-SMSC Register Sets (Rev. 01-11-07)
If “EN FLAGS” has been executed and P25 is set to a one:; IBF is inverted and gated onto MIRQ. The
MIRQ signal can be connected to system interrupt to signify that the LPC47M172 CPU has read the DBB
register. If “EN FLAGS” has not been executed, MIRQ is controlled by P25, Writing a zero to P25 forces
MIRQ low, a high forces MIRQ high. (MIRQ is normally selected as IRQ12 for mouse support).
Gate A20
A general purpose P21 is used as a software controlled Gate A20 or user defined output.
8042 PINS
The 8042 functions P17, P16 and P12 are not supported in LPC47M172.
Industry-standard PC-AT-compatible keyboards employ a two-wire, bidirectional TTL interface for data
transmission. Several sources also supply PS/2 mouse products that employ the same type of interface.
To facilitate system expansion, the LPC47M172 provides four signal pins that may be used to implement
this interface directly for an external keyboard and mouse.
The LPC47M172 has four high-drive, open-drain output, bidirectional port pins that can be used for
external serial interfaces, such as external keyboard and PS/2-type mouse interfaces. They are KCLK,
KDAT, MCLK, and MDAT. P26 is inverted and output as KCLK. The KCLK pin is connected to TEST0.
P27 is inverted and output as KDAT. The KDAT pin is connected to P10. P23 is inverted and output as
MCLK. The MCLK pin is connected to TEST1. P22 is inverted and output as MDAT. The MDAT pin is
connected to P11.
External pull-ups may be required.
The keyboard provides support for two power-saving modes: soft powerdown mode and hard powerdown
mode. In soft powerdown mode, the clock to the ALU is stopped but the timer/counter and interrupts are
still active. In hard power down mode the clock to the 8042 is stopped.
This mode is entered by executing a HALT instruction. The execution of program code is halted until
either RESET is driven active or a data byte is written to the DBBIN register by a master CPU. If this
mode is exited using the interrupt, and the IBF interrupt is enabled, then program execution resumes with
a CALL to the interrupt routine, otherwise the next instruction is executed. If it is exited using RESET then
a normal reset sequence is initiated and program execution starts from program memory location 0.
This mode is entered by executing a STOP instruction.
oscillator driver cell. When either RESET is driven active or a data byte is written to the DBBIN register
by a master CPU, this mode will be exited (as above). However, as the oscillator cell will require an
initialization time, either RESET must be held active for sufficient time to allow the oscillator to stabilize.
Program execution will resume as above.
DATASHEET
Page 116
The oscillator is stopped by disabling the
SMSC LPC47M172