LPC47M172_07 SMSC [SMSC Corporation], LPC47M172_07 Datasheet - Page 91

• Manufacturer Part Number: LPC47M172_07
• Description: Advanced I/O Controller with Motherboard GLUE Logic
• Manufacturer: SMSC [SMSC Corporation]

Note:
7.4
7.4.1
7.4.2
BIT 0 TMOUT - TIME OUT
SMSC LPC47M172
CONNECTOR
(1) = Compatible Mode
(3) = High Speed Mode
For the cable interconnection required for ECP support and the Slave Connector pin numbers, refer to the
IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993.
document is available from Microsoft.
IBM XT/AT Compatible, Bi-Directional and EPP Modes
Data Port
ADDRESS OFFSET = 00H
The Data Port is located at an offset of ‘00H’ from the base address. The data register is cleared at
initialization by RESET. During a WRITE operation, the Data Register latches the contents of the internal
data bus. The contents of this register are buffered (non inverting) and output onto the PD0 - PD7 ports.
During a READ operation in SPP mode, PD0 - PD7 ports are buffered (not latched) and output to the host
CPU.
Status Port
ADDRESS OFFSET = 01H
The Status Port is located at an offset of ‘01H’ from the base address. The contents of this register are
latched for the duration of a read cycle. The bits of the Status Port are defined as follows:
This bit is valid in EPP mode only and indicates that a 10 usec time out has occurred on the EPP bus. A
logic O means that no time out error has occurred; a logic 1 means that a time out error has been
detected. This bit is cleared by a RESET. If the TIMEOUT_SELECT bit (bit 4 of the Parallel Port Mode
Register 2, 0xF1 in Serial Port Logical Device Configuration Registers) is ‘0’, writing a one to this bit clears
the TMOUT status bit. Writing a zero to this bit has no effect. If the TIMEOUT_SELECT bit (bit 4 of the
HOST
2-9
10
11
12
13
14
15
16
17
1
Description of Pin
See Chapter 3
PIN NUMBER
Functions.
SMSC
Table 7.1 - Parallel Port Connector
DATASHEET
nSTROBE
PD<0:7>
nACK
BUSY
PE
SLCT
nALF
nERROR
nINITP
nSLCTIN
STANDARD
Page 91
nWrite
PData<0:7>
Intr
nWait
(User Defined)
(User Defined)
nDatastb
(User Defined)
nRESET
nAddrstrb
Advanced I/O Controller with Motherboard GLUE Logic
EPP
SMSC/Non-SMSC Register Sets (Rev. 01-11-07)
nStrobe
PData<0:7>
nAck
PError,
nAckReverse (3)
Select
nAutoFd,
HostAck(3)
nFault (1)
nPeriphRequest (3)
nInit(1)
nReverseRqst(3)
nSelectIn(1,3)
Busy, PeriphAck(3)
ECP
Datasheet
This