LPC47M172_07 SMSC [SMSC Corporation], LPC47M172_07 Datasheet - Page 148

• Manufacturer Part Number: LPC47M172_07
• Description: Advanced I/O Controller with Motherboard GLUE Logic
• Manufacturer: SMSC [SMSC Corporation]

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
7.40
7.41
SMSC/Non-SMSC Register Sets (Rev. 01-11-07)
Resume Reset Logic
The nRSMRST signal is the reset output for the ICH resume well. This signal is used as a power on reset
signal as well as a brown-out sensor for the ICH.
The rising edge of nRSMRST is a delayed 3.3V buffered copy of V_5P0_STBY. This delay, t
nominally 32ms, starts when V_5P0_STBY hits the trip point, V
high after the t
the t
that V
parameters.
Note that no internal clock is available during nRSMRST generation, so an internally generated delay is
required. The requirements are loose enough that an onboard RC delay is permissible. This delay is only
required at V_5P0_STBY power on and brown-out recovery.
See Table 13.7 for nRSMRST timing.
CNR Logic
The CNR CODEC Down Enable Circuitry is used in conjunction with soft audio and motherboards with a
CNR slot. This feature allows the Basic Input / Output System (BIOS) to enable an audio CNR board. See
figure and table below for implementation and definition of the input and output states. Note that these
signals are required in all sleep states. The CNR circuitry is powered from VTR.
The nCDC_DWN_ENAB pin also functions as a GPIO. This allows BIOS to drive the pin to a known state
if the motherboard requires it. Note that nCDC_DWN_RST still follows the nCDC_DWN_ENAB pin even
when it is functioning as a GPIO output.
The nCDC_DWN_ENAB/GP24 pin functions as follows:
RESET_DELAY
When the nCDC_DWN_ENAB function is selected on GP24, it will be an input to the CNR logic. The
polarity bit will not affect the input.
If GP24 is programmed as GPIO output the GP data bit will control nCDC_DWN_ENAB input to the
CNR logic. The data bit will also be reflected on the GP24 pin as an output under both VCC and VTR
power. The polarity bit will affect the output and input to the CNR logic. The output type select bit will
also affect the GP24 pin.
If GP24 is programmed as GPIO input, it will not affect the nCDC_DWN_ENAB input into the CNR
logic. It will function as a normal GPIO input and can be used as a PME event.
TRIP
nAUD_LNK_RST
nCDC_DWN_ENAB/
GP24
nCDC_DWN_RST
nRSMRST
V_5P0_STBY
shown in Figure 26 has a V
RESET_DELAY
– until VTR (3.3V) goes active. On the falling edge there is minimal delay, t
NAME
NAME
only if VTR (3.3V) is present. Otherwise, nRSMRST will be active low beyond
O8
PWR
BUFFER
I
IO12
O12
TYPE
Table 7.48 - nRSMRST Pin
DATASHEET
Table 7.49 - CNR Pins
TRIP_MIN
VTR
VTR
VTR
POWER
VTR
Page 148
POWER
WELL
WELL
and a V
Resume Reset Output
5V Standby
TRIP_MAX
Audio Link Reset Input
CODEC Down Enable
Input/GPIO
CODEC Down Reset Output
DESCRIPTION
. See Table below for timing and voltage
DESCRIPTION
TRIP
. Note the nRSMRST will be inactive
RESET_FALL
SMSC LPC47M172
RESET_DELAY
. Note
,