LPC47M172_07 SMSC [SMSC Corporation], LPC47M172_07 Datasheet - Page 42

• Manufacturer Part Number: LPC47M172_07
• Description: Advanced I/O Controller with Motherboard GLUE Logic
• Manufacturer: SMSC [SMSC Corporation]

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
BIT 6 MOTOR ENABLE 2
BIT 7 MOTOR ENABLE 3
6.4.6
Normal Floppy Mode
Enhanced Floppy Mode 2 (OS2)
SMSC/Non-SMSC Register Sets (Rev. 01-11-07)
REG 3F3
REG 3F3 Reserved Reserved
The MTR2 disk interface output is not supported in the LPC47M172.
The MTR3 disk interface output is not supported in the LPC47M172.
Tape Drive Register (TDR)
Address 3F3 READ/WRITE
The Tape Drive Register (TDR) is included for 82077 software compatibility and allows the user to assign
tape support to a particular drive during initialization. Any future references to that drive automatically
invokes tape support. The TDR Tape Select bits TDR.[1:0] determine the tape drive number. Table 6.5
illustrates the Tape Select Bit encoding. Note that drive 0 is the boot device and cannot be assigned tape
support.
unaffected by a software reset.
Normal mode.Register 3F3 contains only bits 0 and 1. When this register is read, bits 2 – 7 are ‘0’.
Register 3F3 for Enhanced Floppy Mode 2 operation.
Bit 5
X
1
0
DIGITAL OUTPUT
The remaining Tape Drive Register bits TDR.[7:2] are tristated when read.
DB7
DB7
Bit 4
REGISTER
0
X
1
0
Table 6.4 - Internal 2 Drive Decode - Drives 0 and 1 Swapped
Bit1
0
0
X
DB6
DB6
0
TAPE SEL1
(TDR.1)
Bit 0
0
1
X
0
0
1
1
Table 6.5 - Tape Select Bits
DRIVE SELECT OUTPUTS
DATASHEET
DB5
DB5
Drive Type ID
0
nDS1
0
1
1
(ACTIVE LOW)
TAPE SEL0
(TDR.0)
Page 42
DB4
DB4
0
1
0
1
0
nDS0
1
0
1
Floppy Boot Drive
DB3
DB3
0
SELECTED
DRIVE
None
1
2
3
MOTOR ON OUTPUTS
nMTR1
nBIT 4
nBIT 4
nBIT 4
DB2
DB2
(ACTIVE LOW)
0
tape sel1
tape sel1
DB1
DB1
nMTR0
nBIT 5
nBIT 5
nBIT 5
tape sel0
tape sel0
SMSC LPC47M172
DB0
DB0
The TDR is