LPC47M172_07 SMSC [SMSC Corporation], LPC47M172_07 Datasheet - Page 118

• Manufacturer Part Number: LPC47M172_07
• Description: Advanced I/O Controller with Motherboard GLUE Logic
• Manufacturer: SMSC [SMSC Corporation]

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
7.25.17 External Clock Signal
7.25.18 Default Reset Conditions
Note:
7.25.19 GateA20 and Keyboard Reset
7.26
7.26.1 Port 92 Register
SMSC/Non-SMSC Register Sets (Rev. 01-11-07)
The LPC47M172 Keyboard Controller clock source is a 12 MHz clock generated from a 14.318 MHz clock.
The reset pulse must last for at least 24 16 MHz clock periods. The pulse-width requirement applies to
both internally (Vcc POR) and externally generated reset signals. In powerdown mode, the external clock
signal is not loaded by the chip.
The LPC47M172 has one source of hardware reset: an external reset via the nPCI_RESET pin. Refer to
Table 7.13 for the effect of each type of reset on the internal registers.
N/A: Not Applicable
The LPC47M172 provides two options for GateA20 and Keyboard Reset: 8042 Software Generated
GateA20 and KRESET and Port 92 Fast GateA20 and KRESET.
Port 92 Fast Gatea20 and Keyboard Reset
This port can only be read or written if Port 92 has been enabled via bit 2 of the KRST_GA20 Register
(Keyboard Logical Device, 0xF0) set to 1.
This register is used to support the alternate reset (nALT_RST) and alternate A20 (ALT_A20) functions.
Table 7.13 - Keyboard and Mouse Pin/Register Reset Values
Host I/F Status Reg
Host I/F Data Reg
DESCRIPTION
MDAT
KDAT
MCLK
KCLK
DATASHEET
Page 118
HARDWARE RESET
(nPCI_RESET)
Low
Low
Low
Low
00H
N/A
SMSC LPC47M172