MC68HC908GR4 MOTOROLA [Motorola, Inc], MC68HC908GR4 Datasheet - Page 115

• Manufacturer Part Number: MC68HC908GR4
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

7.6.1 PLL Control Register
MC68HC908GR8 — Rev 4.0
MOTOROLA
NOTES:
$003A
$003B
1. When AUTO = 0, PLLIE is forced clear and is read-only.
2. When AUTO = 0, PLLF and LOCK read as clear.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
Select Register (PMDS)
PLL VCO Select Range
PLL Reference Divider
Register (PMRS)
Address:
The PLL control register (PCTL) contains the interrupt enable and flag
bits, the on/off switch, the base clock selector bit, the prescaler bits, and
the VCO power-of-two range selector bits.
PLLIE — PLL Interrupt Enable Bit
Reset:
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
Figure 7-3. CGMC I/O Register Summary
Freescale Semiconductor, Inc.
This read/write bit enables the PLL to generate an interrupt request
when the LOCK bit toggles, setting the PLL flag, PLLF. When the
AUTO bit in the PLL bandwidth control register (PBWC) is clear,
PLLIE cannot be written and reads as logic 0. Reset clears the PLLIE
bit.
For More Information On This Product,
$0036
PLLIE
VRS7
Bit 7
0
0
0
0
Clock Generator Module (CGMC)
Go to: www.freescale.com
Figure 7-4. PLL Control Register (PCTL)
= Unimplemented
= Unimplemented
VRS6
PLLF
1
0
0
6
0
PLLON
VRS5
0
0
0
5
1
VRS4
BCS
R
0
0
0
4
0
= Reserved
RDS3
VRS3
PRE1
0
0
3
0
Clock Generator Module (CGMC)
RDS2
VRS2
PRE0
0
0
2
0
RDS1
CGMC Registers
VRS1
VPR1
0
0
1
0
Technical Data
RDS0
VRS0
VPR0
Bit 0
0
1
0
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