MC68HC908GR4 MOTOROLA [Motorola, Inc], MC68HC908GR4 Datasheet - Page 221
MC68HC908GR4
Manufacturer Part Number
MC68HC908GR4
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC908GR4.pdf
(408 pages)
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MC68HC908GR8 — Rev 4.0
MOTOROLA
T1CH1 and T1CH0 — Timer 1 Channel I/O Bits
SPSCK — SPI Serial Clock
MOSI — Master Out/Slave In
MISO — Master In/Slave Out
SS — Slave Select
Freescale Semiconductor, Inc.
The PTD5/T1CH1–PTD4/T1CH0 pins are the TIM1 input
capture/output compare pins. The edge/level select bits, ELSxB and
ELSxA, determine whether the PTD5/T1CH1–PTD4/T1CH0 pins are
timer channel I/O pins or general-purpose I/O pins. See
Interface Module
The PTD3/SPSCK pin is the serial clock input of the SPI module.
When the SPE bit is clear, the PTD3/SPSCK pin is available for
general-purpose I/O.
The PTD2/MOSI pin is the master out/slave in terminal of the SPI
module. When the SPE bit is clear, the PTD2/MOSI pin is available
for general-purpose I/O.
The PTD1/MISO pin is the master in/slave out terminal of the SPI
module. When the SPI enable bit, SPE, is clear, the SPI module is
disabled, and the PTD0/SS pin is available for general-purpose I/O.
Data direction register D (DDRD) does not affect the data direction of
port D pins that are being used by the SPI module. However, the
DDRD bits always determine whether reading port D returns the
states of the latches or the states of the pins. See
The PTD0/SS pin is the slave select input of the SPI module. When
the SPE bit is clear, or when the SPI master bit, SPMSTR, is set, the
PTD0/SS pin is available for general-purpose I/O. When the SPI is
enabled, the DDRB0 bit in data direction register B (DDRB) has no
effect on the PTD0/SS pin.
For More Information On This Product,
Go to: www.freescale.com
Input/Output Ports (I/O)
(TIM).
Input/Output Ports (I/O)
Table
Timer
Technical Data
16-5.
Port D
221
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