MC68HC908GR4 MOTOROLA [Motorola, Inc], MC68HC908GR4 Datasheet - Page 344

• Manufacturer Part Number: MC68HC908GR4
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Timer Interface Module (TIM)
22.5.7 Unbuffered PWM Signal Generation
Technical Data
344
NOTE:
increments. Writing $0080 (128) to the TIM channel registers produces
a duty cycle of 128/256 or 50%.
Any output compare channel can generate unbuffered PWM pulses as
described in
because changing the pulse width requires writing the new pulse width
value over the old value currently in the TIM channel registers.
An unsynchronized write to the TIM channel registers to change a pulse
width value could cause incorrect operation for up to two PWM periods.
For example, writing a new value before the counter reaches the old
value but after the counter reaches the new value prevents any compare
during that PWM period. Also, using a TIM overflow interrupt routine to
write a new, smaller pulse width value may cause the compare to be
missed. The TIM may pass the new value before it is written.
Use the following methods to synchronize unbuffered changes in the
PWM pulse width on channel x:
In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable 0%
duty cycle generation and removes the ability of the channel to self-
correct in the event of software error or noise. Toggling on output
compare also can cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
Freescale Semiconductor, Inc.
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When changing to a shorter pulse width, enable channel x output
compare interrupts and write the new value in the output compare
interrupt routine. The output compare interrupt occurs at the end
of the current pulse. The interrupt routine has until the end of the
PWM period to write the new value.
When changing to a longer pulse width, enable TIM overflow
interrupts and write the new value in the TIM overflow interrupt
routine. The TIM overflow interrupt occurs at the end of the current
PWM period. Writing a larger value in an output compare interrupt
routine (at the end of the current pulse) could cause two output
compares to occur in the same PWM period.
Timer Interface Module (TIM)
Go to: www.freescale.com
Pulse Width Modulation
(PWM). The pulses are unbuffered
MC68HC908GR8 — Rev 4.0
MOTOROLA