MC68HC908GR4 MOTOROLA [Motorola, Inc], MC68HC908GR4 Datasheet - Page 243
MC68HC908GR4
Manufacturer Part Number
MC68HC908GR4
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC908GR4.pdf
(408 pages)
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18.5.3.3 Data Sampling
MC68HC908GR8 — Rev 4.0
MOTOROLA
RT CLOCK
RT CLOCK
SAMPLES
PE1/RxD
CLOCK
RESET
STATE
RT
The receiver samples the PE1/RxD pin at the RT clock rate. The RT
clock is an internal signal with a frequency 16 times the baud rate. To
adjust for baud rate mismatch, the RT clock is resynchronized at the
following times (see
To locate the start bit, data recovery logic does an asynchronous search
for a logic 0 preceded by three logic 1s. When the falling edge of a
possible start bit occurs, the RT clock begins to count to 16.
To verify the start bit and to detect noise, data recovery logic takes
samples at RT3, RT5, and RT7.
the start bit verification samples.
Freescale Semiconductor, Inc.
•
•
QUALIFICATION
Figure 18-6. Receiver Data Sampling
For More Information On This Product,
START BIT
After every start bit
After the receiver detects a data bit change from logic 1 to logic 0
(after the majority of data bit samples at RT8, RT9, and RT10
returns a valid logic 1 and the majority of the next RT8, RT9, and
RT10 samples returns a valid logic 0)
Serial Communications Interface (SCI)
Go to: www.freescale.com
VERIFICATION
Figure
START BIT
18-6):
START BIT
SAMPLING
Table 18-2
DATA
Serial Communications Interface (SCI)
summarizes the results of
Functional Description
Technical Data
LSB
243
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