MC68HC908GR4 MOTOROLA [Motorola, Inc], MC68HC908GR4 Datasheet - Page 359

• Manufacturer Part Number: MC68HC908GR4
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

22.10.6 TIM Channel Registers
MC68HC908GR8 — Rev 4.0
MOTOROLA
CHxMAX — Channel x Maximum Duty Cycle Bit
These read/write registers contain the captured TIM counter value of the
input capture function or the output compare value of the output
compare function. The state of the TIM channel registers after reset is
unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the
TIM channel x registers (TCHxH) inhibits input captures until the low
byte (TCHxL) is read.
In output compare mode (MSxB:MSxA 0:0), writing to the high byte of
the TIM channel x registers (TCHxH) inhibits output compares until the
low byte (TCHxL) is written.
PTEx/TCHx
CHxMAX
Freescale Semiconductor, Inc.
When the TOVx bit is at logic 1, setting the CHxMAX bit forces the
duty cycle of buffered and unbuffered PWM signals to 100%. As
CHxMAX Latency
after it is set or cleared. The output stays at the 100% duty cycle level
until the cycle after CHxMAX is cleared.
For More Information On This Product,
OVERFLOW
Timer Interface Module (TIM)
Go to: www.freescale.com
COMPARE
PERIOD
OUTPUT
Figure 22-13. CHxMAX Latency
OVERFLOW
shows, the CHxMAX bit takes effect in the cycle
COMPARE
OUTPUT
OVERFLOW
COMPARE
OUTPUT
Timer Interface Module (TIM)
OVERFLOW
COMPARE
OUTPUT
Technical Data
OVERFLOW
I/O Registers
.
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