MC68HC908GR4 MOTOROLA [Motorola, Inc], MC68HC908GR4 Datasheet - Page 193

• Manufacturer Part Number: MC68HC908GR4
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

V
GND
GND
MC68HC908GR8 — Rev 4.0
MOTOROLA
GND
IRQ
V
V
V
1. External clock is derived by a 32.768 kHz crystal or a 9.8304 MHz off-chip oscillator
2. PTA0 = 1 if serial communication; PTA0 = X if parallel communication
3. PTA1 = 0
4. DNA = does not apply, X = don’t care
TST
or
X
or
DD
DD
DD
Notes:
RESET
GND
V
V
V
V
V
V
V
or
TST
TST
or
TST
DD
DD
DD
DD
serial, PTA1 = 1
$FFFE/
$FFFF
$FFFF
$FFFF
$FFFF
$FFFF
Not
X
X
Table 15-1. Monitor Mode Signal Requirements and Options
OFF
OFF
OFF
OFF
PLL PTB0 PTB1
ON
X
If entering monitor mode with V
CGMOUT frequency is equal to the CGMXCLK frequency and the OSC1
input directly generates internal bus clocks. In this case, the OSC1
signal must have a 50% duty cycle at maximum bus frequency.
If entering monitor mode without high voltage applied on IRQ (condition
set 2 or 3, where applied voltage is either V
X
X
X
X
X
1
parallel communication for security code entry
Freescale Semiconductor, Inc.
For More Information On This Product,
X
X
X
X
X
0
External
Clock
9.8304
9.8304
32.768
Go to: www.freescale.com
MHz
MHz
kHz
X
X
X
Monitor ROM (MON)
(1)
CGMOUT
4.9152
4.9152
4.9152
MHz
MHz
MHz
—
—
0
2.4576
2.4576
2.4576
Freq
MHz
MHz
MHz
Bus
—
—
0
TST
Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
COP
applied on IRQ (condition set 1), the
PTA0 PTA1
DD
X
X
X
X
X
X
1
1
1
Communication
or V
For Serial
X
0
1
0
1
0
1
X
X
SS
Rate
), then all port B pin
Functional Description
Baud
9600
DNA
9600
DNA
9600
DNA
—
—
Monitor ROM (MON)
0
(2) (3)
External frequency
PLL enabled (BCS
Technical Data
No operation until
always divided by
Enters user mode
Enters user mode
an illegal address
— will encounter
PTB0 and PTB1
reset goes high
set) in monitor
voltages only
IRQ = V
Comment
required if
code
reset
4
TST
193