MC68HC908GR4 MOTOROLA [Motorola, Inc], MC68HC908GR4 Datasheet - Page 279

• Manufacturer Part Number: MC68HC908GR4
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

19.4.2.2 Computer Operating Properly (COP) Reset
MC68HC908GR8 — Rev 4.0
MOTOROLA
CGMXCLK
CGMOUT
PORRST
OSC1
RST
IAB
An input to the SIM is reserved for the COP reset signal. The overflow of
the COP counter causes an internal reset and sets the COP bit in the
SIM reset status register (SRSR). The SIM actively pulls down the RST
pin for all internal reset sources.
To prevent a COP module timeout, write any value to location $FFFF.
Writing to location $FFFF clears the COP counter and bits 12 through 4
of the SIM counter. The SIM counter output, which occurs at least every
2
serviced as soon as possible out of reset to guarantee the maximum
amount of time before the first timeout.
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The internal reset signal is asserted.
The SIM enables CGMOUT.
Internal clocks to the CPU and modules are held inactive for 4096
CGMXCLK cycles to allow stabilization of the oscillator.
The RST pin is driven low during the oscillator stabilization time.
The POR bit of the SIM reset status register (SRSR) is set and all
other bits in the register are cleared.
4
CGMXCLK cycles, drives the COP counter. The COP should be
Figure 19-7. POR Recovery
System Integration Module (SIM)
CYCLES
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32
CYCLES
32
$FFFE
System Integration Module (SIM)
Reset and System Initialization
$FFFF
Technical Data
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