MC68HC908GR4 MOTOROLA [Motorola, Inc], MC68HC908GR4 Datasheet - Page 64

• Manufacturer Part Number: MC68HC908GR4
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Resets and Interrupts
4.3.3.3 Low-Voltage Inhibit Reset
4.3.3.4 Illegal Opcode Reset
4.3.3.5 Illegal Address Reset
Technical Data
64
A low-voltage inhibit (LVI) reset is an internal reset caused by a drop in
the power supply voltage to the LVI trip voltage, V
An LVI reset:
An illegal opcode reset is an internal reset caused by an opcode that is
not in the instruction set. An illegal opcode reset sets the ILOP bit in the
SIM reset status register.
If the stop enable bit, STOP, in the mask option register is a logic 0, the
STOP instruction causes an illegal opcode reset.
An illegal address reset is an internal reset caused by opcode fetch from
an unmapped address. An illegal address reset sets the ILAD bit in the
SIM reset status register.
A data fetch from an unmapped address does not generate a reset.
Freescale Semiconductor, Inc.
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For More Information On This Product,
Holds the clocks to the CPU and modules inactive for an oscillator
stabilization delay of 4096 CGMXCLK cycles after the power
supply voltage rises to V
Drives the RST pin low for as long as V
during the oscillator stabilization delay
Releases the RST pin 32 CGMXCLK cycles after the oscillator
stabilization delay
Releases the CPU to begin the reset vector sequence
64 CGMXCLK cycles after the oscillator stabilization delay
Sets the LVI bit in the SIM reset status register
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Resets and Interrupts
TRIPF
DD
MC68HC908GR8 — Rev 4.0
is below V
TRIPF
.
TRIPF
MOTOROLA
and