LM3S6611-IQC20-A0T ETC2 [List of Unclassifed Manufacturers], LM3S6611-IQC20-A0T Datasheet - Page 16

• Manufacturer Part Number: LM3S6611-IQC20-A0T
• Description: Microcontroller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

Table of Contents
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Ethernet Controller ...................................................................................................................... 367
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Analog Comparators ................................................................................................................... 411
Register 1:
Register 2:
Register 3:
Register 4:
16
I
I
I
I
I
I
I
I
I
I
Ethernet MAC Raw Interrupt Status (MACRIS), offset 0x000 ............................................ 376
Ethernet MAC Interrupt Acknowledge (MACIACK), offset 0x000 ....................................... 378
Ethernet MAC Interrupt Mask (MACIM), offset 0x004 ....................................................... 379
Ethernet MAC Receive Control (MACRCTL), offset 0x008 ................................................ 380
Ethernet MAC Transmit Control (MACTCTL), offset 0x00C ............................................... 381
Ethernet MAC Data (MACDATA), offset 0x010 ................................................................. 382
Ethernet MAC Individual Address 0 (MACIA0), offset 0x014 ............................................. 384
Ethernet MAC Individual Address 1 (MACIA1), offset 0x018 ............................................. 385
Ethernet MAC Threshold (MACTHR), offset 0x01C .......................................................... 386
Ethernet MAC Management Control (MACMCTL), offset 0x020 ........................................ 387
Ethernet MAC Management Divider (MACMDV), offset 0x024 .......................................... 388
Ethernet MAC Management Transmit Data (MACMTXD), offset 0x02C ............................. 389
Ethernet MAC Management Receive Data (MACMRXD), offset 0x030 .............................. 390
Ethernet MAC Number of Packets (MACNP), offset 0x034 ............................................... 391
Ethernet MAC Transmission Request (MACTR), offset 0x038 ........................................... 392
Ethernet PHY Management Register 0 – Control (MR0), address 0x00 ............................. 393
Ethernet PHY Management Register 1 – Status (MR1), address 0x01 .............................. 395
Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2), address 0x02 ................. 397
Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3), address 0x03 ................. 398
Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4), address
0x04 ............................................................................................................................. 399
Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability
(MR5), address 0x05 ..................................................................................................... 401
Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6), address
0x06 ............................................................................................................................. 402
Ethernet PHY Management Register 16 – Vendor-Specific (MR16), address 0x10 ............. 403
Ethernet PHY Management Register 17 – Interrupt Control/Status (MR17), address
0x11 .............................................................................................................................. 405
Ethernet PHY Management Register 18 – Diagnostic (MR18), address 0x12 ..................... 407
Ethernet PHY Management Register 19 – Transceiver Control (MR19), address 0x13 ....... 408
Ethernet PHY Management Register 23 – LED Configuration (MR23), address 0x17 ......... 409
Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24), address 0x18 .......... 410
Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00 .................................... 416
Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04 ......................................... 417
Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 ........................................... 418
Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 ......................... 419
2
2
2
2
2
2
2
2
2
2
C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 355
C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 356
C Master Configuration (I2CMCR), offset 0x020 ............................................................ 357
C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 359
C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 360
C Slave Data (I2CSDR), offset 0x008 ........................................................................... 362
C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 363
C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 364
C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 365
C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 366
Preliminary
October 09, 2007