LM3S6611-IQC20-A0T ETC2 [List of Unclassifed Manufacturers], LM3S6611-IQC20-A0T Datasheet - Page 390

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LM3S6611-IQC20-A0T

Manufacturer Part Number
LM3S6611-IQC20-A0T
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
Ethernet Controller
Ethernet MAC Management Receive Data (MACMRXD)
Base 0x4004.8000
Offset 0x030
Type R/W, reset 0x0000.0000
390
Reset
Reset
Type
Type
Bit/Field
31:16
15:0
R/W
RO
31
15
0
0
Register 13: Ethernet MAC Management Receive Data (MACMRXD), offset
0x030
This register holds the last value read from the MII Management registers.
R/W
RO
30
14
0
0
reserved
MDRX
Name
R/W
RO
29
13
0
0
R/W
RO
28
12
0
0
R/W
RO
Type
27
11
R/W
0
0
RO
R/W
RO
26
10
0
0
Reset
0x0
0x0
R/W
RO
25
0
9
0
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
MII Register Receive Data
The MDRX bits represent the data that was read in the previous MII
management transaction.
R/W
RO
24
0
8
0
reserved
MDRX
R/W
RO
23
0
7
0
R/W
RO
22
0
6
0
R/W
RO
21
0
5
0
R/W
RO
20
0
4
0
R/W
RO
19
0
3
0
R/W
RO
18
0
2
0
October 09, 2007
R/W
RO
17
0
1
0
R/W
RO
16
0
0
0

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