LM3S6611-IQC20-A0T ETC2 [List of Unclassifed Manufacturers], LM3S6611-IQC20-A0T Datasheet - Page 368

• Manufacturer Part Number: LM3S6611-IQC20-A0T
• Description: Microcontroller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

Ethernet Controller
15.1
15.2
15.2.1
368
Block Diagram
Figure 15-1. Ethernet Controller Block Diagram
Functional Description
As shown in Figure 15-2 on page 368, the Ethernet Controller is functionally divided into two layers
or modules: the Media Access Controller (MAC) layer and the Network Physical (PHY) layer. These
correspond to the OSI model layers 2 and 1. The primary interface to the Ethernet Controller is a
simple bus interface to the MAC layer. The MAC layer provides transmit and receive processing for
Ethernet frames. The MAC layer also provides the interface to the PHY module via an internal Media
Independent Interface (MII).
Figure 15-2. Ethernet Controller
Internal MII Operation
For the MII management interface to function properly, the MDIO signal must be connected through
a 10k Ω pull-up resistor to the +3.3 V supply. Failure to connect this pull-up resistor will prevent
management transactions on this internal MII to function. Note that it is possible for data transmission
across the MII to still function since the PHY layer will auto-negotiate the link parameters by default.
System Clock
Interrupt
Cortex M3
Individual
Interrupt
Address
Control
MACIACK
MACIAR0
MACIAR1
MACISR
MACIMR
Transmit
MACMDVR
MACMDRX
Receive
MACMDTX
Control
Control
Control
Access
MACITHR
MACMCR
MACRCR
MACNPR
MACTCR
MACTRR
MACMAR
MACDR
Data
MII
Media Access
Controller
(Layer 2)
MAC
Preliminary
Ethernet Controller
Transmit
Receive
FIFO
FIFO
Layer Entity
(Layer 1)
Physical
PHY
Media Independent Interface
Decoding
Management Register Set
Encoding
Transmit
Collision
Receive
Detect
MR0
MR1
MR2
MR3
MR16
MR17
MR4
MR5
MR6
Recovery
Shaping
Carrier
Sense
Pulse
Clock
MR18
MR19
MR23
MR24
Magnetics
Negotiation
Reference
MDIX
Clock
October 09, 2007
Auto
TXOP
TXON
XTLN
RJ45
XTLP
RXIP
RXIN