LM3S6611-IQC20-A0T ETC2 [List of Unclassifed Manufacturers], LM3S6611-IQC20-A0T Datasheet - Page 378

• Manufacturer Part Number: LM3S6611-IQC20-A0T
• Description: Microcontroller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

Ethernet Controller
Ethernet MAC Interrupt Acknowledge (MACIACK)
Base 0x4004.8000
Offset 0x000
Type W1C, reset 0x0000.0000
378
Reset
Reset
Type
Type
Bit/Field
31:7
6
5
4
3
2
1
0
RO
RO
31
15
0
0
Register 2: Ethernet MAC Interrupt Acknowledge (MACIACK), offset 0x000
A write of a 1 to any bit position of this register clears the corresponding interrupt bit in the Ethernet
MAC Raw Interrupt Status (MACRIS) register.
RO
RO
30
14
0
0
reserved
PHYINT
TXEMP
MDINT
RXINT
Name
RXER
TXER
FOV
RO
RO
29
13
0
0
RO
RO
28
12
0
0
reserved
RO
RO
W1C
W1C
W1C
W1C
W1C
W1C
W1C
Type
27
11
0
0
RO
RO
RO
26
10
0
0
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
RO
RO
25
0
9
0
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Clear PHY Interrupt
A write of a 1 clears the PHYINT interrupt read from the MACRIS
register.
Clear MII Transaction Complete
A write of a 1 clears the MDINT interrupt read from the MACRIS register.
Clear Receive Error
A write of a 1 clears the RXER interrupt read from the MACRIS register.
Clear FIFO Overrun
A write of a 1 clears the FOV interrupt read from the MACRIS register.
Clear Transmit FIFO Empty
A write of a 1 clears the TXEMP interrupt read from the MACRIS register.
Clear Transmit Error
A write of a 1 clears the TXER interrupt read from the MACRIS register
and resets the TX FIFO write pointer.
Clear Packet Received
A write of a 1 clears the RXINT interrupt read from the MACRIS register.
RO
RO
24
0
8
0
reserved
RO
RO
23
0
7
0
PHYINT
W1C
RO
22
0
6
0
MDINT
W1C
RO
21
0
5
0
RXER
W1C
RO
20
0
4
0
W1C
FOV
RO
19
0
3
0
TXEMP
W1C
RO
18
0
2
0
October 09, 2007
TXER
W1C
RO
17
0
1
0
RXINT
W1C
RO
16
0
0
0