LM3S6611-IQC20-A0T ETC2 [List of Unclassifed Manufacturers], LM3S6611-IQC20-A0T Datasheet - Page 273

• Manufacturer Part Number: LM3S6611-IQC20-A0T
• Description: Microcontroller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

UART Control (UARTCTL)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x030
Type R/W, reset 0x0000.0300
October 09, 2007
Reset
Reset
Type
Type
Bit/Field
31:10
6:3
9
8
7
RO
RO
31
15
0
0
Register 8: UART Control (UARTCTL), offset 0x030
The UARTCTL register is the control register. All the bits are cleared on reset except for the
Transmit Enable (TXE) and Receive Enable (RXE) bits, which are set to 1.
To enable the UART module, the UARTEN bit must be set to 1. If software requires a configuration
change in the module, the UARTEN bit must be cleared before the configuration changes are written.
If the UART is disabled during a transmit or receive operation, the current transaction is completed
prior to the UART stopping.
RO
RO
30
14
0
0
reserved
reserved
Name
RXE
TXE
LBE
RO
RO
29
13
0
0
reserved
RO
RO
28
12
0
0
RO
RO
Type
27
11
R/W
R/W
R/W
0
0
RO
RO
RO
RO
26
10
0
0
Reset
0
1
1
0
0
RXE
R/W
RO
25
0
9
1
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Receive Enable
If this bit is set to 1, the receive section of the UART is enabled. When
the UART is disabled in the middle of a receive, it completes the current
character before stopping.
Note:
UART Transmit Enable
If this bit is set to 1, the transmit section of the UART is enabled. When
the UART is disabled in the middle of a transmission, it completes the
current character before stopping.
Note:
UART Loop Back Enable
If this bit is set to 1, the UnTX path is fed through the UnRX path.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
TXE
R/W
RO
24
0
8
1
reserved
R/W
LBE
RO
23
0
7
0
To enable reception, the UARTEN bit must also be set.
To enable transmission, the UARTEN bit must also be set.
RO
RO
22
0
6
0
RO
RO
21
0
5
0
reserved
RO
RO
20
0
4
0
LM3S6611 Microcontroller
RO
RO
19
0
3
0
SIRLP
R/W
RO
18
0
2
0
SIREN
R/W
RO
17
0
1
0
UARTEN
R/W
RO
16
0
0
0
273