LM3S6611-IQC20-A0T ETC2 [List of Unclassifed Manufacturers], LM3S6611-IQC20-A0T Datasheet - Page 382

• Manufacturer Part Number: LM3S6611-IQC20-A0T
• Description: Microcontroller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

Ethernet Controller
Read-Only Register
Ethernet MAC Data (MACDATA)
Base 0x4004.8000
Offset 0x010
Type RO, reset 0x0000.0000
Write-Only Register
Ethernet MAC Data (MACDATA)
Base 0x4004.8000
Offset 0x010
Type WO, reset 0x0000.0000
382
Reset
Reset
Reset
Reset
Type
Type
Type
Type
Bit/Field
31:0
WO
WO
RO
RO
31
15
31
15
0
0
0
0
Register 6: Ethernet MAC Data (MACDATA), offset 0x010
This register enables software to access the TX and RX FIFOs.
Reads from this register return the data stored in the RX FIFO from the location indicated by the
read pointer.
Writes to this register store the data in the TX FIFO at the location indicated by the write pointer.
The write pointer is then auto-incremented to the next TX FIFO location.
There is no mechanism for randomly accessing bytes in either the RX or TX FIFOs. Data must be
read from the RX FIFO sequentially and stored in a buffer for further processing. Once a read has
been performed, the data in the FIFO cannot be re-read. Data must be written to the TX FIFO
sequentially. If an error is made in placing the frame into the TX FIFO, the write pointer can be reset
to the start of the TX FIFO by writing the TXER bit of the MACIACK register and then the data
re-written.
WO
WO
RO
RO
30
14
30
14
0
0
0
0
RXDATA
Name
WO
WO
RO
RO
29
13
29
13
0
0
0
0
WO
WO
RO
RO
28
12
28
12
0
0
0
0
WO
WO
RO
RO
Type
27
11
27
11
0
0
0
0
RO
WO
WO
RO
RO
26
10
26
10
0
0
0
0
Reset
0x0
WO
WO
RO
RO
25
25
0
9
0
0
9
0
Preliminary
Description
Receive FIFO Data
The RXDATA bits represent the next four bytes of data stored in the RX
FIFO.
WO
WO
RO
RO
24
24
0
8
0
0
8
0
RXDATA
RXDATA
TXDATA
TXDATA
WO
WO
RO
RO
23
23
0
7
0
0
7
0
WO
WO
RO
RO
22
22
0
6
0
0
6
0
WO
WO
RO
RO
21
21
0
5
0
0
5
0
WO
WO
RO
RO
20
20
0
4
0
0
4
0
WO
WO
RO
RO
19
19
0
3
0
0
3
0
WO
WO
RO
RO
18
18
0
2
0
0
2
0
October 09, 2007
WO
WO
RO
RO
17
17
0
1
0
0
1
0
WO
WO
RO
RO
16
16
0
0
0
0
0
0