LM3S6611-IQC20-A0T ETC2 [List of Unclassifed Manufacturers], LM3S6611-IQC20-A0T Datasheet - Page 379

• Manufacturer Part Number: LM3S6611-IQC20-A0T
• Description: Microcontroller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

Ethernet MAC Interrupt Mask (MACIM)
Base 0x4004.8000
Offset 0x004
Type R/W, reset 0x0000.007F
October 09, 2007
Reset
Reset
Type
Type
Bit/Field
31:7
6
5
4
3
2
1
0
RO
RO
31
15
0
0
Register 3: Ethernet MAC Interrupt Mask (MACIM), offset 0x004
This register allows software to enable/disable Ethernet MAC interrupts. Writing a 0 disables the
interrupt, while writing a 1 enables it.
RO
RO
30
14
0
0
PHYINTM
TXEMPM
reserved
MDINTM
RXINTM
RXERM
TXERM
FOVM
Name
RO
RO
29
13
0
0
RO
RO
28
12
0
0
reserved
RO
RO
Type
27
11
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
RO
RO
RO
26
10
0
0
Reset
0x0
1
1
1
1
1
1
1
RO
RO
25
0
9
0
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Mask PHY Interrupt
This bit masks the PHYINT bit in the MACRIS register from being
asserted.
Mask MII Transaction Complete
This bit masks the MDINT bit in the MACRIS register from being
asserted.
Mask Receive Error
This bit masks the RXER bit in the MACRIS register from being asserted.
Mask FIFO Overrrun
This bit masks the FOV bit in the MACRIS register from being asserted.
Mask Transmit FIFO Empty
This bit masks the TXEMP bit in the MACRIS register from being
asserted.
Mask Transmit Error
This bit masks the TXER bit in the MACRIS register from being asserted.
Mask Packet Received
This bit masks the RXINT bit in the MACRIS register from being
asserted.
RO
RO
24
0
8
0
reserved
RO
RO
23
0
7
0
PHYINTM
R/W
RO
22
0
6
1
MDINTM
R/W
RO
21
0
5
1
RXERM
R/W
RO
20
0
4
1
LM3S6611 Microcontroller
FOVM
R/W
RO
19
0
3
1
TXEMPM
R/W
RO
18
0
2
1
TXERM
R/W
RO
17
0
1
1
RXINTM
R/W
RO
16
0
0
1
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