LM3S6611-IQC20-A0T ETC2 [List of Unclassifed Manufacturers], LM3S6611-IQC20-A0T Datasheet - Page 219

• Manufacturer Part Number: LM3S6611-IQC20-A0T
• Description: Microcontroller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

GPTM Interrupt Clear (GPTMICR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x024
Type W1C, reset 0x0000.0000
October 09, 2007
Reset
Reset
Type
Type
Bit/Field
31:11
7:4
10
9
8
RO
RO
31
15
0
0
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024
This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. Writing a 1
to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS registers.
RO
RO
30
14
0
0
TBTOCINT
CBMCINT
CBECINT
reserved
reserved
reserved
Name
RO
RO
29
13
0
0
RO
RO
28
12
0
0
RO
RO
W1C
W1C
W1C
Type
27
11
0
0
RO
RO
CBECINT
W1C
RO
26
10
0
0
Reset
0x00
CBMCINT
0x0
0
0
0
W1C
RO
25
0
9
0
Preliminary
TBTOCINT
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM CaptureB Event Interrupt Clear
The CBECINT values are defined as follows:
GPTM CaptureB Match Interrupt Clear
The CBMCINT values are defined as follows:
GPTM TimerB Time-Out Interrupt Clear
The TBTOCINT values are defined as follows:
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
W1C
RO
Value
Value
Value
24
0
8
0
reserved
0
1
0
1
0
1
Description
The interrupt is unaffected.
The interrupt is cleared.
Description
The interrupt is unaffected.
The interrupt is cleared.
Description
The interrupt is unaffected.
The interrupt is cleared.
RO
RO
23
0
7
0
RO
RO
22
0
6
0
reserved
RO
RO
21
0
5
0
RO
RO
20
0
4
0
RTCCINT
LM3S6611 Microcontroller
W1C
RO
19
0
3
0
CAECINT
W1C
RO
18
0
2
0
CAMCINT
W1C
RO
17
0
1
0
TATOCINT
W1C
RO
16
0
0
0
219