LM3S6611-IQC20-A0T ETC2 [List of Unclassifed Manufacturers], LM3S6611-IQC20-A0T Datasheet - Page 70

• Manufacturer Part Number: LM3S6611-IQC20-A0T
• Description: Microcontroller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

System Control
Run-Mode Clock Configuration (RCC)
Base 0x400F.E000
Offset 0x060
Type R/W, reset 0x07A0.3AD1
70
Reset
Reset
Type
Type
Bit/Field
31:28
27
RO
RO
31
15
0
0
reserved
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060
This register is defined to provide source control and frequency speed.
RO
RO
30
14
0
0
reserved
reserved
Name
PWRDN
ACG
R/W
RO
29
13
0
1
reserved
RO
RO
28
12
0
1
BYPASS
ACG
R/W
R/W
Type
27
11
R/W
0
1
RO
reserved
R/W
RO
26
10
1
0
Reset
0x0
0
R/W
R/W
25
1
9
1
SYSDIV
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Auto Clock Gating
This bit specifies whether the system uses the Sleep-Mode Clock
Gating Control (SCGCn) registers and Deep-Sleep-Mode Clock
Gating Control (DCGCn) registers if the controller enters a Sleep or
Deep-Sleep mode (respectively). If set, the SCGCn or DCGCn registers
are used to control the clocks distributed to the peripherals when the
controller is in a sleep mode. Otherwise, the Run-Mode Clock Gating
Control (RCGCn) registers are used when the controller enters a sleep
mode.
The RCGCn registers are always used to control the clocks in Run
mode.
This allows peripherals to consume less power when the controller is
in a sleep mode and the peripheral is unused.
R/W
R/W
24
1
8
0
XTAL
R/W
R/W
23
1
7
1
USESYSDIV
R/W
R/W
22
0
6
1
R/W
RO
21
0
5
0
OSCSRC
R/W
RO
20
0
4
1
RO
RO
19
0
3
0
reserved
reserved
RO
RO
18
0
2
0
October 09, 2007
IOSCDIS
R/W
RO
17
0
1
0
MOSCDIS
R/W
RO
16
0
0
1