LM3S6611-IQC20-A0T ETC2 [List of Unclassifed Manufacturers], LM3S6611-IQC20-A0T Datasheet - Page 376

• Manufacturer Part Number: LM3S6611-IQC20-A0T
• Description: Microcontroller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

Ethernet Controller
Ethernet MAC Raw Interrupt Status (MACRIS)
Base 0x4004.8000
Offset 0x000
Type RO, reset 0x0000.0000
376
Reset
Reset
Type
Type
Bit/Field
31:7
6
5
4
3
2
RO
RO
31
15
0
0
Register 1: Ethernet MAC Raw Interrupt Status (MACRIS), offset 0x000
The MACRIS register is the interrupt status register. On a read, this register gives the current status
value of the corresponding interrupt prior to masking.
RO
RO
30
14
0
0
reserved
PHYINT
TXEMP
MDINT
Name
RXER
FOV
RO
RO
29
13
0
0
RO
RO
28
12
0
0
reserved
RO
RO
Type
27
11
0
0
RO
RO
RO
RO
RO
RO
RO
RO
26
10
0
0
Reset
0x0
0x0
0x0
0x0
0x0
0x0
RO
RO
25
0
9
0
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PHY Interrupt
When set, indicates that an enabled interrupt in the PHY layer has
occured. MR17 in the PHY must be read to determine the specific PHY
event that triggered this interrupt.
MII Transaction Complete
When set, indicates that a transaction (read or write) on the MII interface
has completed successfully.
Receive Error
This bit indicates that an error was encountered on the receiver. The
possible errors that can cause this interrupt bit to be set are:
■
■
■
■
FIFO Overrrun
When set, indicates that an overrun was encountered on the receive
FIFO.
Transmit FIFO Empty
When set, indicates that the packet was transmitted and that the TX
FIFO is empty.
RO
RO
24
0
8
0
reserved
A receive error occurs during the reception of a frame (100 Mb/s
only).
The frame is not an integer number of bytes (dribble bits) due to an
alignment error.
The CRC of the frame does not pass the FCS check.
The length/type field is inconsistent with the frame data size when
interpreted as a length field.
RO
RO
23
0
7
0
PHYINT
RO
RO
22
0
6
0
MDINT
RO
RO
21
0
5
0
RXER
RO
RO
20
0
4
0
FOV
RO
RO
19
0
3
0
TXEMP
RO
RO
18
0
2
0
October 09, 2007
TXER
RO
RO
17
0
1
0
RXINT
RO
RO
16
0
0
0