LM3S6611-IQC20-A0T ETC2 [List of Unclassifed Manufacturers], LM3S6611-IQC20-A0T Datasheet - Page 207

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LM3S6611-IQC20-A0T

Manufacturer Part Number
LM3S6611-IQC20-A0T
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
GPTM Configuration (GPTMCFG)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x000
Type R/W, reset 0x0000.0000
October 09, 2007
Reset
Reset
Type
Type
Bit/Field
31:3
2:0
RO
RO
31
15
0
0
Register 1: GPTM Configuration (GPTMCFG), offset 0x000
This register configures the global operation of the GPTM module. The value written to this register
determines whether the GPTM is in 32- or 16-bit mode.
RO
RO
30
14
0
0
GPTMCFG
reserved
Name
RO
RO
29
13
0
0
RO
RO
28
12
0
0
RO
RO
Type
27
11
R/W
0
0
RO
RO
RO
26
10
0
0
Reset
0x00
0x0
reserved
RO
RO
25
0
9
0
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM Configuration
The GPTMCFG values are defined as follows:
RO
RO
0x4-0x7
24
0
8
0
Value
reserved
0x0
0x1
0x2
0x3
RO
RO
23
0
7
0
Description
32-bit timer configuration.
32-bit real-time clock (RTC) counter configuration.
Reserved.
Reserved.
16-bit timer configuration, function is controlled by bits 1:0 of
GPTMTAMR and GPTMTBMR.
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
LM3S6611 Microcontroller
RO
RO
19
0
3
0
R/W
RO
18
0
2
0
GPTMCFG
R/W
RO
17
0
1
0
R/W
RO
16
0
0
0
207

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