LM3S6611-IQC20-A0T ETC2 [List of Unclassifed Manufacturers], LM3S6611-IQC20-A0T Datasheet - Page 300

• Manufacturer Part Number: LM3S6611-IQC20-A0T
• Description: Microcontroller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

Synchronous Serial Interface (SSI)
13.2.4.4 Freescale SPI Frame Format with SPO=0 and SPH=1
13.2.4.5 Freescale SPI Frame Format with SPO=1 and SPH=0
300
The transfer signal sequence for Freescale SPI format with SPO=0 and SPH=1 is shown in Figure
13-6 on page 300, which covers both single and continuous transfers.
Figure 13-6. Freescale SPI Frame Format with SPO=0 and SPH=1
SSIClk
SSIFss
Note:
In this configuration, during idle periods:
■
■
■
■
■
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low. The master SSITx output is enabled. After
a further one half SSIClk period, both master and slave valid data is enabled onto their respective
transmission lines. At the same time, the SSIClk is enabled with a rising edge transition.
Data is then captured on the falling edges and propagated on the rising edges of the SSIClk signal.
In the case of a single word transfer, after all bits have been transferred, the SSIFss line is returned
to its idle High state one SSIClk period after the last bit has been captured.
For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words
and termination is the same as that of the single word transfer.
Single and continuous transmission signal sequences for Freescale SPI format with SPO=1 and
SPH=0 are shown in Figure 13-7 on page 301 and Figure 13-8 on page 301.
SSIRx
SSITx
SSIClk is forced Low
SSIFss is forced High
The transmit data line SSITx is arbitrarily forced Low
When the SSI is configured as a master, it enables the SSIClk pad
When the SSI is configured as a slave, it disables the SSIClk pad
Q is undefined.
Q
MSB
MSB
Preliminary
4 to 16 bits
LSB
LSB
Q
October 09, 2007